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path: root/drivers/net/phy
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2021-04-21net: phy: marvell: don't use empty switch default caseMarek Behún
This causes error reported by kernel test robot. Signed-off-by: Marek Behún <kabel@kernel.org> Fixes: 41d26bf4aba0 ("net: phy: marvell: refactor HWMON OOP style") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20net: phy: at803x: fix probe error if copper page is selectedMichael Walle
The commit c329e5afb42f ("net: phy: at803x: select correct page on config init") selects the copper page during probe. This fails if the copper page was already selected. In this case, the value of the copper page (which is 1) is propagated through phy_restore_page() and is finally returned for at803x_probe(). Fix it, by just using the at803x_page_write() directly. Also in case of an error, the regulator is not disabled and leads to a WARN_ON() when the probe fails. This couldn't happen before, because at803x_parse_dt() was the last call in at803x_probe(). It is hard to see, that the parse_dt() actually enables the regulator. Thus move the regulator_enable() to the probe function and undo it in case of an error. Fixes: c329e5afb42f ("net: phy: at803x: select correct page on config init") Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: David Bauer <mail@david-bauer.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20phy: nxp-c45-tja11xx: fix phase offset calculationRadu Pirea (NXP OSS)
Fix phase offset calculation. Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20net: phy: marvell: add support for Amethyst internal PHYMarek Behún
Add support for Amethyst internal PHY. The only difference from Peridot is HWMON. Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20net: phy: marvell: use assignment by bitwise AND operatorMarek Behún
Use the &= operator instead of ret = ret & ... Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20net: phy: marvell: fix HWMON enable register for 6390Marek Behún
Register 27_6.15:14 has the following description in 88E6393X documentation: Temperature Sensor Enable 0x0 - Sample every 1s 0x1 - Sense rate decided by bits 10:8 of this register 0x2 - Use 26_6.5 (One shot Temperature Sample) to enable 0x3 - Disable This is compatible with how the 6390 code uses this register currently, but the 6390 code handles it as two 1-bit registers (somewhat), instead of one register with 4 possible values. (A newer version of the 6390 documentation removed temperature sensor section completely. In an older version, the above mentioned register is reserved, although it is R/W. Since the code works, I think we can assume that it is correct.) Rename this register and define all 4 values according to 6393X documentation. Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20net: phy: marvell: refactor HWMON OOP styleMarek Behún
Use a structure of Marvell PHY specific HWMON methods to reduce code duplication. Store a pointer to this structure into the PHY driver's driver_data member. Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20net: phy: genphy_loopback: add link speed configurationOleksij Rempel
In case of loopback, in most cases we need to disable autoneg support and force some speed configuration. Otherwise, depending on currently active auto negotiated link speed, the loopback may or may not work. This patch was tested with following PHYs: TJA1102, KSZ8081, KSZ9031, AT8035, AR9331. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-20net: phy: execute genphy_loopback() per default on all PHYsOleksij Rempel
The generic loopback is really generic and is defined by the 802.3 standard, we should just mandate that drivers implement a custom loopback if the generic one cannot work. Suggested-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-19phy: nxp-c45: add driver for tja1103Radu Pirea (NXP OSS)
Add driver for tja1103 driver and for future NXP C45 PHYs. Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-19net: phy: add genphy_c45_pma_suspend/resumeRadu Pirea (NXP OSS)
Add generic PMA suspend and resume callback functions for C45 PHYs. Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-17Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c - keep the ZC code, drop the code related to reinit net/bridge/netfilter/ebtables.c - fix build after move to net_generic Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-04-15net: phy: at803x: select correct page on config initDavid Bauer
The Atheros AR8031 and AR8033 expose different registers for SGMII/Fiber as well as the copper side of the PHY depending on the BT_BX_REG_SEL bit in the chip configure register. The driver assumes the copper side is selected on probe, but this might not be the case depending which page was last selected by the bootloader. Notably, Ubiquiti UniFi bootloaders show this behavior. Select the copper page when probing to circumvent this. Signed-off-by: David Bauer <mail@david-bauer.net> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-14net: phy: marvell-88x2222: swap 1G/10G modes on autonegIvan Bornyakov
Setting 10G without autonegotiation is invalid according to phy_ethtool_ksettings_set(). Thus, we need to set it during autonegotiation. If 1G autonegotiation can't complete for quite a time, but there is signal in line, switch line interface type to 10GBase-R, if supported, in hope for link to be established. And vice versa. If 10GBase-R link can't be established for quite a time, and autonegotiation is enabled, and there is signal in line, switch line interface type to appropriate 1G mode, i.e. 1000Base-X or SGMII, if supported. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-14net: phy: marvell-88x2222: move read_status after config_anegIvan Bornyakov
No functional changes, just move read link status routines below autonegotiation configuration to make future functional changes more distinct. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-14net: phy: marvell-88x2222: check that link is operationalIvan Bornyakov
Some SFP modules uses RX_LOS for link indication. In such cases link will be always up, even without cable connected. RX_LOS changes will trigger link_up()/link_down() upstream operations. Thus, check that SFP link is operational before actual read link status. If there is no SFP cage connected to the tranciever, check only PMD Recieve Signal Detect register. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-12net: phy: marvell: fix detection of PHY on Topaz switchesPali Rohár
Since commit fee2d546414d ("net: phy: marvell: mv88e6390 temperature sensor reading"), Linux reports the temperature of Topaz hwmon as constant -75°C. This is because switches from the Topaz family (88E6141 / 88E6341) have the address of the temperature sensor register different from Peridot. This address is instead compatible with 88E1510 PHYs, as was used for Topaz before the above mentioned commit. Create a new mapping table between switch family and PHY ID for families which don't have a model number. And define PHY IDs for Topaz and Peridot families. Create a new PHY ID and a new PHY driver for Topaz's internal PHY. The only difference from Peridot's PHY driver is the HWMON probing method. Prior this change Topaz's internal PHY is detected by kernel as: PHY [...] driver [Marvell 88E6390] (irq=63) And afterwards as: PHY [...] driver [Marvell 88E6341 Family] (irq=63) Signed-off-by: Pali Rohár <pali@kernel.org> BugLink: https://github.com/globalscaletechnologies/linux/issues/1 Fixes: fee2d546414d ("net: phy: marvell: mv88e6390 temperature sensor reading") Reviewed-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-11phy: sfp: add netlink SFP support to generic SFP codeAndrew Lunn
The new netlink API for reading SFP data requires a new op to be implemented. The idea of the new netlink SFP code is that userspace is responsible to parsing the EEPROM data and requesting pages, rather than have the kernel decide what pages are interesting and returning them. This allows greater flexibility for newer formats. Currently the generic SFP code only supports simple SFPs. Allow i2c address 0x50 and 0x51 to be accessed with page and bank must always be 0. This interface will later be extended when for example QSFP support is added. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Vladyslav Tarasiuk <vladyslavt@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-09Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Conflicts: MAINTAINERS - keep Chandrasekar drivers/net/ethernet/mellanox/mlx5/core/en_main.c - simple fix + trust the code re-added to param.c in -next is fine include/linux/bpf.h - trivial include/linux/ethtool.h - trivial, fix kdoc while at it include/linux/skmsg.h - move to relevant place in tcp.c, comment re-wrapped net/core/skmsg.c - add the sk = sk // sk = NULL around calls net/tipc/crypto.c - trivial Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-04-09net: phy: make PHY PM ops a no-op if MAC driver manages PHY PMHeiner Kallweit
Resume callback of the PHY driver is called after the one for the MAC driver. The PHY driver resume callback calls phy_init_hw(), and this is potentially problematic if the MAC driver calls phy_start() in its resume callback. One issue was reported with the fec driver and a KSZ8081 PHY which seems to become unstable if a soft reset is triggered during aneg. The new flag allows MAC drivers to indicate that they take care of suspending/resuming the PHY. Then the MAC PM callbacks can handle any dependency between MAC and PHY PM. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-04-08net: phy: marvell10g: change module descriptionMarek Behún
This module supports not only Alaska X, but also Alaska M. Change module description appropriately. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: differentiate 88E2110 vs 88E2111Marek Behún
88E2111 is a variant of 88E2110 which does not support 5 gigabit speeds. Differentiate these variants via the match_phy_device() method, since they have the same PHY ID. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: fix driver name for mv88e2110Marek Behún
The driver name "mv88x2110" should be instead "mv88e2110". Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: add separate structure for 88X3340Marek Behún
The 88X3340 contains 4 cores similar to 88X3310, but there is a difference: it does not support xaui host mode. Instead the corresponding MACTYPE means rxaui / 5gbase-r / 2500base-x / sgmii without AN Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: support other MACTYPEsMarek Behún
Currently the only "changing" MACTYPE we support is when the PHY changes between 10gbase-r / 5gbase-r / 2500base-x / sgmii Add support for usxgmii xaui / 5gbase-r / 2500base-x / sgmii rxaui / 5gbase-r / 2500base-x / sgmii and also 5gbase-r / 2500base-x / sgmii for 88E2110. Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: store temperature read method in chip strucutreMarek Behún
Now that we have a chip structure, we can store the temperature reading method in this structure (OOP style). Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: check for correct supported interface modeMarek Behún
The 88E2110 does not support xaui nor rxaui modes. Check for correct interface mode for different chips. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: support all rate matching modesMarek Behún
Add support for all rate matching modes for 88X3310 (currently only 10gbase-r is supported, but xaui and rxaui can also be used). Add support for rate matching for 88E2110 (on 88E2110 the MACTYPE register is at a different place). Currently rate matching mode is selected by strapping pins (by setting the MACTYPE register). There is work in progress to enable this driver to deduce the best MACTYPE from the knowledge of which interface modes are supported by the host, but this work is not finished yet. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: add MACTYPE definitions for 88E21xxMarek Behún
Add all MACTYPE definitions for 88E2110, 88E2180, 88E2111 and 88E2181. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: add all MACTYPE definitions for 88X33x0Marek Behún
Add all MACTYPE definitions for 88X3310, 88X3310P, 88X3340 and 88X3340P. In order to have consistent naming, rename MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH to MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: indicate 88X33x0 only port control registersMarek Behún
Rename port control registers to indicate that they are valid only for 88X33x0, not for 88E21x0. Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: allow 5gbase-r and usxgmiiMarek Behún
These modes are also supported by these PHYs. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: fix typoMarek Behún
This space should be a tab instead. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-08net: phy: marvell10g: rename registerMarek Behún
The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to MV_V2_PORT_CTRL_MACTYPE_*. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-01net: phy: broadcom: Add statistics for all Gigabit PHYsFlorian Fainelli
All Gigabit PHYs use the same register layout as far as fetching statistics goes. Fast Ethernet PHYs do not all support statistics, and the BCM54616S would require some switching between the coper and fiber modes to fetch the appropriate statistics which is not supported yet. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-30net: phy: broadcom: Only advertise EEE for supported modesFlorian Fainelli
We should not be advertising EEE for modes that we do not support, correct that oversight by looking at the PHY device supported linkmodes. Fixes: 99cec8a4dda2 ("net: phy: broadcom: Allow enabling or disabling of EEE") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-30net: phy: remove repeated wordPeng Li
Remove repeated word "to". Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-30net: phy: lan87xx: fix access to wrong register of LAN87xxAndre Edich
The function lan87xx_config_aneg_ext was introduced to configure LAN95xxA but as well writes to undocumented register of LAN87xx. This fix prevents that access. The function lan87xx_config_aneg_ext gets more suitable for the new behavior name. Reported-by: Måns Rullgård <mans@mansr.com> Fixes: 05b35e7eb9a1 ("smsc95xx: add phylib support") Signed-off-by: Andre Edich <andre.edich@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-29net: phy: Correct function name mdiobus_register_board_info() in commentYang Yingliang
Fix the following make W=1 kernel build warning: drivers/net/phy/mdio-boardinfo.c:63: warning: expecting prototype for mdio_register_board_info(). Prototype was for mdiobus_register_board_info() instead Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-25Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netDavid S. Miller
Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-24net: phy: marvell10g: Add PHY loopback supportWong Vee Khee
Add support for PHY loopback for Marvell 88x2110 and Marvell 88x3310. This allow user to perform PHY loopback test using ethtool selftest. Signed-off-by: Wong Vee Khee <vee.khee.wong@linux.intel.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-24net: phy: add genphy_c45_loopbackWong Vee Khee
Add generic code to enable C45 PHY loopback into the common phy-c45.c file. This will allow C45 PHY drivers aceess this by setting .set_loopback. Suggested-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Wong Vee Khee <vee.khee.wong@linux.intel.com> Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-19net: phy: mscc: coma mode disabled for VSC8584Bjarni Jonasson
This patch releases coma mode for VSC8584 as done for VSC8514 in commit ca0d7fd0a58d ("net: phy: mscc: coma mode disabled for VSC8514") Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.") Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-19net: phy: mscc: improved serdes calibration applied to VSC8584Bjarni Jonasson
Introduced 'FOJI' serdes calibration in commit 85e97f0b984e ("net: phy: mscc: improved serdes calibration applied to VSC8514") Now including the VSC8584 family. Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.") Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-19net: phy: mscc: Applying LCPLL reset to VSC8584Bjarni Jonasson
Introduced LCPLL reset in commit d15e08d9fb82 ("net: phy: mscc: adding LCPLL reset to VSC8514"). Now applying this reset to the VSC8584 phy familiy. Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.") Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-19net: phy: at803x: remove at803x_aneg_done()Michael Walle
Here is what Vladimir says about it: at803x_aneg_done() keeps the aneg reporting as "not done" even when the copper-side link was reported as up, but the in-band autoneg has not finished. That was the _intended_ behavior when that code was introduced, and Heiner have said about it [1]: | That's not nice from the PHY: | It signals "link up", and if the system asks the PHY for link details, | then it sheepishly says "well, link is *almost* up". If the specification of phy_aneg_done behavior does not include in-band autoneg (and it doesn't), then this piece of code does not belong here. The fact that we can no longer trigger this code from phylib is yet another reason why it fails at its intended (and wrong) purpose and should be removed. Removing the SGMII link check, would just keep the call to genphy_aneg_done(), which is also the fallback. Thus we can just remove at803x_aneg_done() altogether. [1] https://lore.kernel.org/netdev/fdf0074a-2572-5914-6f3e-77202cbf96de@gmail.com/ Suggested-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-15net: phy: add Marvell 88X2222 transceiver supportIvan Bornyakov
Add basic support for the Marvell 88X2222 multi-speed ethernet transceiver. This PHY provides data transmission over fiber-optic as well as Twinax copper links. The 88X2222 supports 2 ports of 10GBase-R and 1000Base-X on the line-side interface. The host-side interface supports 4 ports of 10GBase-R, RXAUI, 1000Base-X and 2 ports of XAUI. This driver, however, supports only XAUI on the host-side and 1000Base-X/10GBase-R on the line-side, for now. The SGMII is also supported over 1000Base-X. Interrupts are not supported. Internal registers access compliant with the Clause 45 specification. Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-15net: phylink: Fix phylink_err() function name error in phylink_major_configOng Boon Leong
if pl->mac_ops->mac_finish() failed, phylink_err should use "mac_finish" instead of "mac_prepare". Fixes: b7ad14c2fe2d4 ("net: phylink: re-implement interface configuration with PCS") Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-15net: phylink: make phylink_parse_mode() support non-DT platformOng Boon Leong
Certain platform does not support DT, so we make phylink_parse_mode() to allow non-DT platform to use it to setup in-band AN advertising. Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-03-12net: phy: broadcom: Fix RGMII delays for BCM50160 and BCM50610MFlorian Fainelli
The PHY driver entry for BCM50160 and BCM50610M calls bcm54xx_config_init() but does not call bcm54xx_config_clock_delay() in order to configuration appropriate clock delays on the PHY, fix that. Fixes: 733336262b28 ("net: phy: Allow BCM5481x PHYs to setup internal TX/RX clock delay") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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