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path: root/drivers/mailbox/imx-mailbox.c
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2019-11-30mailbox: imx: add support for imx v1 muRichard Zhu
There is a version 1.0 MU on i.MX7ULP platform. One new version ID register is added, and it's offset is 0. TRn registers are defined at the offset 0x20 ~ 0x2C. RRn registers are defined at the offset 0x40 ~ 0x4C. SR/CR registers are defined at 0x60/0x64. Extend this driver to support it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-30mailbox: imx: Clear the right interrupts at shutdownDaniel Baluta
Make sure to only clear enabled interrupts keeping count of the connection type. Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-30mailbox: imx: Fix Tx doorbell shutdown pathDaniel Baluta
Tx doorbell is handled by txdb_tasklet and doesn't have an associated IRQ. Anyhow, imx_mu_shutdown ignores this and tries to free an IRQ that wasn't requested for Tx DB resulting in the following warning: [ 1.967644] Trying to free already-free IRQ 26 [ 1.972108] WARNING: CPU: 2 PID: 157 at kernel/irq/manage.c:1708 __free_irq+0xc0/0x358 [ 1.980024] Modules linked in: [ 1.983088] CPU: 2 PID: 157 Comm: kworker/2:1 Tainted: G [ 1.993524] Hardware name: Freescale i.MX8QXP MEK (DT) [ 1.998668] Workqueue: events deferred_probe_work_func [ 2.003812] pstate: 60000085 (nZCv daIf -PAN -UAO) [ 2.008607] pc : __free_irq+0xc0/0x358 [ 2.012364] lr : __free_irq+0xc0/0x358 [ 2.016111] sp : ffff00001179b7e0 [ 2.019422] x29: ffff00001179b7e0 x28: 0000000000000018 [ 2.024736] x27: ffff000011233000 x26: 0000000000000004 [ 2.030053] x25: 000000000000001a x24: ffff80083bec74d4 [ 2.035369] x23: 0000000000000000 x22: ffff80083bec7588 [ 2.040686] x21: ffff80083b1fe8d8 x20: ffff80083bec7400 [ 2.046003] x19: 0000000000000000 x18: ffffffffffffffff [ 2.051320] x17: 0000000000000000 x16: 0000000000000000 [ 2.056637] x15: ffff0000111296c8 x14: ffff00009179b517 [ 2.061953] x13: ffff00001179b525 x12: ffff000011142000 [ 2.067270] x11: ffff000011129f20 x10: ffff0000105da970 [ 2.072587] x9 : 00000000ffffffd0 x8 : 0000000000000194 [ 2.077903] x7 : 612065657266206f x6 : ffff0000111e7b09 [ 2.083220] x5 : 0000000000000003 x4 : 0000000000000000 [ 2.088537] x3 : 0000000000000000 x2 : 00000000ffffffff [ 2.093854] x1 : 28b70f0a2b60a500 x0 : 0000000000000000 [ 2.099173] Call trace: [ 2.101618] __free_irq+0xc0/0x358 [ 2.105021] free_irq+0x38/0x98 [ 2.108170] imx_mu_shutdown+0x90/0xb0 [ 2.111921] mbox_free_channel.part.2+0x24/0xb8 [ 2.116453] mbox_free_channel+0x18/0x28 This bug is present from the beginning of times. Cc: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: imx: Clear GIEn bit at shutdownDaniel Baluta
GIEn is enabled at startup for RX doorbell mailboxes so we need to clear the bit at shutdown in order to avoid leaving the interrupt line enabled. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-05-09mailbox: imx: use devm_platform_ioremap_resource() to simplify codeAnson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-03-11mailbox: imx: keep MU irq working during suspend/resumeAnson Huang
During noirq suspend phase, mailbox MU irq will be masked but many drivers still need to communicate with system controller firmware via mailbox, if MU irq is masked, it will cause RPC timeout as below: [ 23.372103] imx-scu scu: RPC send msg timeout Setting MU irq to be wakeup source is NOT working as GIC driver does NOT have .irq_set_wake implemented, so to support suspend/resume, just make imx mailbox driver NOT suspend, since MU is always a wakeup source on i.MX platforms with system controller inside, and its power/clock is maintained by system controller, mailbox driver no need to manage them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-12-21mailbox: imx: Use device-managed registration APIThierry Reding
Get rid of some boilerplate driver removal code by using the newly added device-managed registration API. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2018-08-15mailbox: Add support for i.MX messaging unitOleksij Rempel
The i.MX Messaging Unit is a two side block which allows applications implement communication over this sides. The MU includes the following features: - Messaging control by interrupts or by polling - Four general-purpose interrupt requests reflected to the other side - Three general-purpose flags reflected to the other side - Four receive registers with maskable interrupt - Four transmit registers with maskable interrupt Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>