summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm
AgeCommit message (Collapse)Author
2015-08-26drm/rockchip: vop: support plane scaleMark Yao
Win_full support 1/8 to 8 scale down/up engine, support all format scale. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-08-26drm/rockchip: vop: restore vop registers when resumeMark Yao
The registers will be reset to default values when whole power domain off, so restore registers from regsbak. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-08-26drm/rockchip: vop: Default enable win2/3 area0 bitMark Yao
Win2/3 support multiple area function, but we haven't found a suitable way to use it yet, so let's just use them as other windows with only area 0 enabled. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-08-26drm/rockchip: vop: Add yuv plane supportMark Yao
vop support yuv with NV12, NV16 and NV24, only 2 plane yuv. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-08-26drm/rockchip: vop: Fix window dest start pointMark Yao
Dest start point use crtc_x/y is wrong, crtc_x/y is not equal to dest.x1/y1 at plane scale. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-08-26drm/rockchip: vop: Fix virtual stride calculationMark Yao
vir_stride need number words of the virtual width, and fb->pitches save bytes_per_pixel, so just div 4 switch to stride. Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
2015-08-25Revert "drm/atomic: Call ww_acquire_done after check phase is complete"Dave Airlie
This reverts commit 992cbf19b32900efa17850b9fa0031fd623edd4d. Until we make fbdev layer atomic we can't call this. Requested-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com? Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-08-24Merge tag 'v4.2-rc8' into drm-nextDave Airlie
Linux 4.2-rc8 Backmerge required for Intel so they can fix their -next tree up properly.
2015-08-24drm/mgag200: Add support for a new rev of G200eMathieu Larouche
- Added PLL algorithm for a new rev of G200e - Removed the bandwidth limitation for the new G200e Signed-off-by: Mathieu Larouche <mathieu.larouche@matrox.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-08-24drm/mgag200: Add support for a new G200eW3 chipsetMathieu Larouche
- Added support for the new deviceID for G200eW3 - Added PLL algorithm for the G200eW3 - Added some initialization code for G200eW3 Signed-off-by: Mathieu Larouche <mathieu.larouche@matrox.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-08-21drm/radeon: fix hotplug race at startupDave Airlie
We apparantly get a hotplug irq before we've initialised modesetting, [drm] Loading R100 Microcode BUG: unable to handle kernel NULL pointer dereference at (null) IP: [<c125f56f>] __mutex_lock_slowpath+0x23/0x91 *pde = 00000000 Oops: 0002 [#1] Modules linked in: radeon(+) drm_kms_helper ttm drm i2c_algo_bit backlight pcspkr psmouse evdev sr_mod input_leds led_class cdrom sg parport_pc parport floppy intel_agp intel_gtt lpc_ich acpi_cpufreq processor button mfd_core agpgart uhci_hcd ehci_hcd rng_core snd_intel8x0 snd_ac97_codec ac97_bus snd_pcm usbcore usb_common i2c_i801 i2c_core snd_timer snd soundcore thermal_sys CPU: 0 PID: 15 Comm: kworker/0:1 Not tainted 4.2.0-rc7-00015-gbf67402 #111 Hardware name: MicroLink /D850MV , BIOS MV85010A.86A.0067.P24.0304081124 04/08/2003 Workqueue: events radeon_hotplug_work_func [radeon] task: f6ca5900 ti: f6d3e000 task.ti: f6d3e000 EIP: 0060:[<c125f56f>] EFLAGS: 00010282 CPU: 0 EIP is at __mutex_lock_slowpath+0x23/0x91 EAX: 00000000 EBX: f5e900fc ECX: 00000000 EDX: fffffffe ESI: f6ca5900 EDI: f5e90100 EBP: f5e90000 ESP: f6d3ff0c DS: 007b ES: 007b FS: 0000 GS: 0000 SS: 0068 CR0: 8005003b CR2: 00000000 CR3: 36f61000 CR4: 000006d0 Stack: f5e90100 00000000 c103c4c1 f6d2a5a0 f5e900fc f6df394c c125f162 f8b0faca f6d2a5a0 c138ca00 f6df394c f7395600 c1034741 00d40000 00000000 f6d2a5a0 c138ca00 f6d2a5b8 c138ca10 c1034b58 00000001 f6d40000 f6ca5900 f6d0c940 Call Trace: [<c103c4c1>] ? dequeue_task_fair+0xa4/0xb7 [<c125f162>] ? mutex_lock+0x9/0xa [<f8b0faca>] ? radeon_hotplug_work_func+0x17/0x57 [radeon] [<c1034741>] ? process_one_work+0xfc/0x194 [<c1034b58>] ? worker_thread+0x18d/0x218 [<c10349cb>] ? rescuer_thread+0x1d5/0x1d5 [<c103742a>] ? kthread+0x7b/0x80 [<c12601c0>] ? ret_from_kernel_thread+0x20/0x30 [<c10373af>] ? init_completion+0x18/0x18 Code: 42 08 e8 8e a6 dd ff c3 57 56 53 83 ec 0c 8b 35 48 f7 37 c1 8b 10 4a 74 1a 89 c3 8d 78 04 8b 40 08 89 63 Reported-and-Tested-by: Meelis Roos <mroos@linux.ee> Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-08-21drm/dp/mst: dump branch OUI in debugfs (v2)Dave Airlie
It appears some MST docks are worse than other, but the only way to know is to see the sw revisions in here, so dump the branch OUI so we can look at the sw revision. v2: Thierry made me feel guilty, so I parsed the branch OUI. Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-08-21Merge tag 'drm-intel-fixes-2015-08-20' of ↵Dave Airlie
git://anongit.freedesktop.org/drm-intel into drm-fixes Revert of a VBT parsing commit that should've been queued for drm-next, not v4.2. The revert unbreaks Braswell among other things. Also on Braswell removal of DP HBR2/TP3 and intermediate eDP frequency support. The code was optimistically added based on incorrect documentation; the platform does not support them. These are cc: stable. Finally a gpu state fix from Chris, also cc: stable. * tag 'drm-intel-fixes-2015-08-20' of git://anongit.freedesktop.org/drm-intel: drm/i915: Avoid TP3 on CHV drm/i915: remove HBR2 from chv supported list Revert "drm/i915: Add eDP intermediate frequencies for CHV" Revert "drm/i915: Allow parsing of variable size child device entries from VBT" drm/i915: Flag the execlists context object as dirty after every use
2015-08-20Merge branch 'drm-next-fsl-dcu' of ↵Dave Airlie
https://github.com/Jianwei-Wang/linux-drm-fsl-dcu into drm-next Merge Freescale DCU FRM driver. * 'drm-next-fsl-dcu' of https://github.com/Jianwei-Wang/linux-drm-fsl-dcu: MAINTAINERS: Add Freescale DCU DRM driver maintainer devicetree: Add NEC to the vendor-prefix list drm/layerscape: Add Freescale DCU DRM driver
2015-08-19drm/layerscape: Add Freescale DCU DRM driverJianwei Wang
This patch add support for Two Dimensional Animation and Compositing Engine (2D-ACE) on the Freescale SoCs. 2D-ACE is a Freescale display controller. 2D-ACE describes the functionality of the module extremely well its name is a value that cannot be used as a token in programming languages. Instead the valid token "DCU" is used to tag the register names and function names. The Display Controller Unit (DCU) module is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. A wide range of panel sizes is supported and the timing of the interface signals is highly configurable. Graphics are read directly from memory and then blended in real-time, which allows for dynamic content creation with minimal CPU intervention. The features: (1) Full RGB888 output to TFT LCD panel. (2) Blending of each pixel using up to 4 source layers dependent on size of panel. (3) Each graphic layer can be placed with one pixel resolution in either axis. (4) Each graphic layer support RGB565 and RGB888 direct colors without alpha channel and BGRA8888 BGRA4444 ARGB1555 direct colors with an alpha channel and YUV422 format. (5) Each graphic layer support alpha blending with 8-bit resolution. This is a simplified version, only one primary plane, one framebuffer, one crtc, one connector and one encoder for TFT LCD panel. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-08-20Merge branch 'drm-atmel-hlcdc-devel' of ↵Dave Airlie
https://github.com/bbrezillon/linux-at91 into drm-next The following PR add support for 3 more atmel SoCs and for some missing features (new input formats and PRIME support). * 'drm-atmel-hlcdc-devel' of https://github.com/bbrezillon/linux-at91: drm: atmel-hlcdc: add support for sama5d4 SoCs drm: atmel-hlcdc: add support for at91sam9n12 SoC drm: atmel-hlcdc: add support for at91sam9x5 SoCs drm: atmel-hlcdc: add RGB565 and RGB444 output support drm: atmel-hlcdc: add the missing DRM_ATOMIC flag drm: atmel-hlcdc: add PRIME support
2015-08-19drm/i915: Avoid TP3 on CHVThulasimani,Sivakumar
This patch removes TP3 support on CHV since there is no support for HBR2 on this platform. v2: rename the function to indicate it checks source rates (Jani) v3: update comment to indicate TP3 dependency on HBR2 supported hardware (Jani) Cc: stable@vger.kernel.org # v4.1+ Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> [Jani: fixed a couple of checkpatch warnings.] Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-08-19drm/i915: remove HBR2 from chv supported listThulasimani,Sivakumar
This patch removes 5.4Gbps from supported link rate for CHV since it is not supported in it. v2: change the ordering for better readability (Ville) Cc: stable@vger.kernel.org # v4.1+ Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-08-19Revert "drm/i915: Add eDP intermediate frequencies for CHV"Thulasimani,Sivakumar
This reverts commit fe51bfb95c996733150c44d21e1c9f4b6322a326. Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Thu Mar 12 17:10:38 2015 +0200 CHV does not support intermediate frequencies so reverting the patch that added it in the first place Cc: stable@vger.kernel.org # v4.1+ Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-08-19Revert "drm/i915: Allow parsing of variable size child device entries from VBT"Jani Nikula
This reverts commit 047fe6e6db9161e69271f56daaafdaf2add023b1 Author: David Weinehall <david.weinehall@linux.intel.com> Date: Tue Aug 4 16:55:52 2015 +0300 drm/i915: Allow parsing of variable size child device entries from VBT That commit is not valid for v4.2, however it will be valid for v4.3. It was simply queued too early. The referenced regressing commit is just fine until the size of struct common_child_dev_config changes, and that won't happen until v4.3. Indeed, the expected size checks here rely on the increased size of the struct, breaking new platforms. Fixes: 047fe6e6db91 ("drm/i915: Allow parsing of variable size child device entries from VBT") Cc: Daniel Vetter <daniel@ffwll.ch> Cc: David Weinehall <david.weinehall@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2015-08-18drm: atmel-hlcdc: add support for sama5d4 SoCsBoris Brezillon
Describe capabilities of the HLCDC IP found on sama5d4 SoCs and add a new entry to the atmel_hlcdc_of_match table. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-08-18drm: atmel-hlcdc: add support for at91sam9n12 SoCBoris Brezillon
Describe capabilities of the HLCDC IP found on at91sam9n12 SoC and add a new entry to the atmel_hlcdc_of_match table. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-08-18drm: atmel-hlcdc: add support for at91sam9x5 SoCsBoris Brezillon
Describe capabilities of the HLCDC IP found on at91sam9x5 SoCs and add a new entry to the atmel_hlcdc_of_match table. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-08-18drm: atmel-hlcdc: add RGB565 and RGB444 output supportBoris Brezillon
The HLCDC IP supports RGB565 and RGB444 output formats. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-08-18drm: atmel-hlcdc: add the missing DRM_ATOMIC flagBoris Brezillon
The atmel-hlcdc driver already supports atomic operations, add the missing DRM_ATOMIC flag to expose the atomic features to userspace. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-08-18drm: atmel-hlcdc: add PRIME supportBoris Brezillon
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2015-08-18drm/atmel-hlcdc: Compile suspend/resume for PM_SLEEP onlyThierry Reding
If PM is enabled but PM_SLEEP is disabled, the suspend/resume functions are still unused and produce a compiler warning. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: <stable@vger.kernel.org> # 4.1+
2015-08-17drm/amdgpu: wait on page directory changes. v2Bas Nieuwenhuizen
Pagetables can be moved and therefore the page directory update can be necessary for the current cs even if none of the the bo's are moved. In that scenario there is no fence between the sdma0 and gfx ring, so we add one. v2 (chk): rebased Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: Select BACKLIGHT_LCD_SUPPORTThierry Reding
Explicitly select BACKLIGHT_LCD_SUPPORT to satisfy the direct dependency of BACKLIGHT_CLASS_DEVICE. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/radeon: Select BACKLIGHT_LCD_SUPPORTThierry Reding
Explicitly select BACKLIGHT_LCD_SUPPORT to satisfy the direct dependency of BACKLIGHT_CLASS_DEVICE. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: cleanup sheduler rq handling v2Christian König
Rework run queue implementation, especially remove the odd list handling. v2: cleanup the code only, no algorithem change. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2015-08-17drm/amdgpu: move prepare work out of scheduler to cs_ioctlChunming Zhou
Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
2015-08-17drm/amdgpu: fix unnecessary wake upChunming Zhou
decrease CPU extra overhead. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
2015-08-17drm/amdgpu: fix duplicated mapping invoke bugmonk.liu
fix the bug that there is duplicated bo_update_mapping issued Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-17drm/amdgpu: drop bo_list_clone when no schedulermonk.liu
bo_list_clone() will take a lot of time when bo_list hold too much elements, like above 7000 Signed-off-by: Monk.Liu <monk.liu@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
2015-08-17drm/amdgpu: disable GPU reset by defaultAlex Deucher
It's not validated yet and causes more harm than good. Avoids spurious resets. Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: fix type mismatch errormonk.liu
remaining timeout returned by amdgpu_fence_wait_any can be larger than max int value, thus the truncated 32 bit value in r ends up being negative while its original long value is positive. Signed-off-by: monk.liu <monk.liu@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Jammy Zhou <jammy.zhou@amd.com>
2015-08-17drm/amdgpu: add reference for **fenceChunming Zhou
fix fence is released when pass to **fence sometimes. add reference for it. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian K?nig <christian.koenig@amd.com>
2015-08-17drm/amdgpu: fix waiting for all fences before flippingChristian König
Otherwise we might see corruption. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: fix UVD return code checkingChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Tested-and-Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-08-17drm/amdgpu: remove scheduler fence list v2Christian König
Unused and missing proper locking. v2: add locking comment to commit message. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> (v1)
2015-08-17drm/amdgpu: remove amd_sched_wait_emit v2Christian König
Not used any more. v2: remove amd_sched_emit as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2015-08-17drm/amdgpu: remove unecessary scheduler fence callbacksChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2015-08-17drm/amdgpu: fix scheduler fence implementationChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2015-08-17drm/amdgpu: don't grab dev->struct_mutex in pm functionsDaniel Vetter
Similar to radeon, except that amdgpu doesn't even use struct_mutex to protect anything like the shared z buffer (sane gpu architecture, yay!). And the code already grabs the globa adev->ring_lock, so this code can't race with itself. Which makes struct_mutex completely redundnant. Remove it. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: Don't take dev->struct_mutex in bo_force_deleteDaniel Vetter
It really doesn't protect anything which doesn't have other locks already. Also this is run from driver unload code so not much need for locks anyway. Same changes as for radeon really. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/radeon: Don't take dev->struct_mutex in pm functionsDaniel Vetter
We already grab 2 device-global locks (write-sema rdev->pm.mclk_lock and rdev->ring_lock), adding another global mutex won't serialize this code more. And since there's really nothing interesting that gets protected in radeon by dev->struct mutex (we only have the global z buffer owners and it's still serializing gem bo destruction in the drm core - which is irrelevant since radeon uses ttm anyway internally) this doesn't add protection. Remove it. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/radeon: Don't take dev->struct_mutex in bo_force_deleteDaniel Vetter
It really doesn't protect anything which doesn't have other locks already. Also this is run from driver unload code so not much need for locks anyway. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-17drm/amdgpu: remove VI hw bug workaround v3Christian König
The workaround simply doesn't work because VM mappings are controlled by userspace not the kernel. Additional to that this is just a performance problem which happens if you have holes in your VM mapping. v2: adjust virtual addr alignment as well. v3: fix trivial warning Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> (v1) Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> (v2)
2015-08-17drm/amdgpu: cleanup amdgpu_fence_ring_wait_seqChristian König
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 23:22:12 +0000