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path: root/drivers/gpu/drm/tegra/dc.c
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2018-07-09driver core: Rename flag AUTOREMOVE to AUTOREMOVE_CONSUMERVivek Gautam
Now that we want to add another flag to autoremove the device link on supplier unbind, it's fair to rename the existing flag from DL_FLAG_AUTOREMOVE to DL_FLAG_AUTOREMOVE_CONSUMER so that we can add similar flag for supplier later. And, while we are touching device.h, fix a doc build warning. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-05-18drm/tegra: dc: Support rotation propertyThierry Reding
Currently only the DRM_MODE_REFLECT_Y rotation is supported. The driver already supports reflection on the Y axis via a custom flag which is not very useful because it requires custom userspace. Add the standard rotation property that supports 0 degree rotation and Y axis reflection for primary and overlay planes to provide a better interface than the custom flag. v2: keep custom flag for ABI compatibility (Dmitry) Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17drm/tegra: dc: Rename supports_blending to has_legacy_blendingDmitry Osipenko
Older Tegra chips do support blending as well. Rename the SoC info entry .supports_blending to .has_legacy_blending to eliminate the confusion. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17drm/tegra: plane: Implement zpos plane property for older TegrasDmitry Osipenko
Older Tegra's do not support plane's Z position handling in hardware, but the hardware provides knobs to implement it in software. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17drm/tegra: dc: Enable plane scaling filtersDmitry Osipenko
Currently resized plane produces a "pixelated" image which doesn't look nice, especially in a case of a video overlay. Enable scaling filters that significantly improve image quality of a scaled overlay. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17drm/tegra: Refactor IOMMU attach/detachThierry Reding
Attaching to and detaching from an IOMMU uses the same code sequence in every driver, so factor it out into separate helpers. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-04drm/tegra: dc: Free syncpoint on errorsThierry Reding
If an error happens during display controller initialization, the host1x syncpoint previously requested would be leaked. Properly clean up the syncpoint along with the other resources. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-04drm/tegra: dc: Balance IOMMU group refcountingDmitry Osipenko
Remove unneeded iommu_group_get() and add missing iommu_group_put(), correcting IOMMU group refcount. This is a minor correction / cleanup that doesn't really fix anything because Tegra's IOMMU driver are built-in and hence groups refcounting can't hold IOMMU driver from unloading. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-04-02Merge tag 'drm-for-v4.17' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds
Pull drm updates from Dave Airlie: "Cannonlake and Vega12 support are probably the two major things. This pull lacks nouveau, Ben had some unforseen leave and a few other blockers so we'll see how things look or maybe leave it for this merge window. core: - Device links to handle sound/gpu pm dependency - Color encoding/range properties - Plane clipping into plane check helper - Backlight helpers - DP TP4 + HBR3 helper support amdgpu: - Vega12 support - Enable DC by default on all supported GPUs - Powerplay restructuring and cleanup - DC bandwidth calc updates - DC backlight on pre-DCE11 - TTM backing store dropping support - SR-IOV fixes - Adding "wattman" like functionality - DC crc support - Improved DC dual-link handling amdkfd: - GPUVM support for dGPU - KFD events for dGPU - Enable PCIe atomics for dGPUs - HSA process eviction support - Live-lock fixes for process eviction - VM page table allocation fix for large-bar systems panel: - Raydium RM68200 - AUO G104SN02 V2 - KEO TX31D200VM0BAA - ARM Versatile panels i915: - Cannonlake support enabled - AUX-F port support added - Icelake base enabling until internal milestone of forcewake support - Query uAPI interface (used for GPU topology information currently) - Compressed framebuffer support for sprites - kmem cache shrinking when GPU is idle - Avoid boosting GPU when waited item is being processed already - Avoid retraining LSPCON link unnecessarily - Decrease request signaling latency - Deprecation of I915_SET_COLORKEY_NONE - Kerneldoc and compiler warning cleanup for upcoming CI enforcements - Full range ycbcr toggling - HDCP support i915/gvt: - Big refactor for shadow ppgtt - KBL context save/restore via LRI cmd (Weinan) - Properly unmap dma for guest page (Changbin) vmwgfx: - Lots of various improvements etnaviv: - Use the drm gpu scheduler - prep work for GC7000L support vc4: - fix alpha blending - Expose perf counters to userspace pl111: - Bandwidth checking/limiting - Versatile panel support sun4i: - A83T HDMI support - A80 support - YUV plane support - H3/H5 HDMI support omapdrm: - HPD support for DVI connector - remove lots of static variables msm: - DSI updates from 10nm / SDM845 - fix for race condition with a3xx/a4xx fence completion irq - some refactoring/prep work for eventual a6xx support (ie. when we have a userspace) - a5xx debugfs enhancements - some mdp5 fixes/cleanups to prepare for eventually merging writeback - support (ie. when we have a userspace) tegra: - mmap() fixes for fbdev devices - Overlay plane for hw cursor fix - dma-buf cache maintenance support mali-dp: - YUV->RGB conversion support rockchip: - rk3399/chromebook fixes and improvements rcar-du: - LVDS support move to drm bridge - DT bindings for R8A77995 - Driver/DT support for R8A77970 tilcdc: - DRM panel support" * tag 'drm-for-v4.17' of git://people.freedesktop.org/~airlied/linux: (1646 commits) drm/i915: Fix hibernation with ACPI S0 target state drm/i915/execlists: Use a locked clear_bit() for synchronisation with interrupt drm/i915: Specify which engines to reset following semaphore/event lockups drm/i915/dp: Write to SET_POWER dpcd to enable MST hub. drm/amdkfd: Use ordered workqueue to restore processes drm/amdgpu: Fix acquiring VM on large-BAR systems drm/amd/pp: clean header file hwmgr.h drm/amd/pp: use mlck_table.count for array loop index limit drm: Fix uabi regression by allowing garbage mode->type from userspace drm/amdgpu: Add an ATPX quirk for hybrid laptop drm/amdgpu: fix spelling mistake: "asssert" -> "assert" drm/amd/pp: Add new asic support in pp_psm.c drm/amd/pp: Clean up powerplay code on Vega12 drm/amd/pp: Add smu irq handlers for legacy asics drm/amd/pp: Fix set wrong temperature range on smu7 drm/amdgpu: Don't change preferred domian when fallback GTT v5 drm/vmwgfx: Bump version patchlevel and date drm/vmwgfx: use monotonic event timestamps drm/vmwgfx: Unpin the screen object backup buffer when not used drm/vmwgfx: Stricter count of legacy surface device resources ...
2018-03-28drm/tegra: dc: Using NULL instead of plain integerWei Yongjun
Fixes the following sparse warnings: drivers/gpu/drm/tegra/dc.c:2181:69: warning: Using plain integer as NULL pointer Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-28Backmerge tag 'v4.16-rc7' into drm-nextDave Airlie
Linux 4.16-rc7 This was requested by Daniel, and things were getting a bit hard to reconcile, most of the conflicts were trivial though.
2018-03-22drm/tegra: dc: Use correct format array for Tegra124Stefan Agner
Use tegra124_(primary|overlay)_formats for Tegra124, otherwise the count specified in the Tegra124 SoC info structure will be different from the array size and cause a crash. Fixes: 511c7023cf23 ("drm/tegra: dc: Support more formats") Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-21Merge tag 'drm/tegra/for-4.17-rc1' of ↵Dave Airlie
git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.17-rc1 This fixes mmap() for fbdev devices by providing a custom implementation based on the KMS variant. This is a fairly exotic case these days, hence why it is not flagged for stable. There is also support for dedicating one of the overlay planes to serve as a hardware cursor on older Tegra that did support hardware cursors but not RGBA formats for it. Planes will now also export the IN_FORMATS property by supporting the various block-linear tiling modifiers for RGBA pixel formats. Other than that, there's a bit of cleanup of DMA API abuse, use of the private object infrastructure for global state (rather than subclassing atomic state objects) and an implementation of ->{begin,end}_cpu_access callbacks for PRIME exported buffers, which allow users to perform cache maintenance on these buffers. * tag 'drm/tegra/for-4.17-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: prime: Implement ->{begin,end}_cpu_access() drm/tegra: gem: Map pages via the DMA API drm/tegra: hub: Use private object for global state drm/tegra: fb: Properly support linear modifier drm/tegra: plane: Support format modifiers drm/tegra: dc: Dedicate overlay plane to cursor on older Tegra's drm/tegra: plane: Make tegra_plane_get_overlap_index() static drm/tegra: fb: Implement ->fb_mmap() callback drm/tegra: gem: Make __tegra_gem_mmap() available more widely drm/tegra: gem: Reshuffle declarations
2018-03-19drm/tegra: dc: Detach IOMMU group from domain only onceThierry Reding
Detaching from an IOMMU group multiple times can lead to a crash. This could potentially be fixed in the IOMMU driver, but it's easy to avoid the subsequent detach operations in this driver, so do that as well. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-17drm/tegra: hub: Use private object for global stateThierry Reding
Rather than subclass the global atomic state to store the hub display clock and rate, create a private object and store this data in its state. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-15drm/tegra: plane: Support format modifiersThierry Reding
Pass the list of valid format modifiers to planes upon initialization and implement the ->format_mod_supported() callback so that userspace can query for the valid combinations of formats and modifiers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-15drm/tegra: dc: Dedicate overlay plane to cursor on older Tegra'sDmitry Osipenko
Older Tegra's do not support RGBA format for the cursor, but instead overlay plane could be used for it. Since there is no much use for the overlays on a regular desktop and HW-accelerated cursor is much better than a SW cursor, let's dedicate one overlay plane to the mouse cursor. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-02-15drm/tegra: Handle 64-bit return from drm_crtc_vblank_count()Dhinakaran Pandiyan
570e86963a51 ("drm: Widen vblank count to 64-bits [v3]") changed the return type for drm_crtc_vblank_count() to u64. This could cause potential problems if the return value is used in arithmetic operations with a 32-bit reference HW vblank count. Explicitly typecasting this down to u32 either fixes a potential problem or serves to add clarity in case the implicit typecasting was already correct. Cc: Keith Packard <keithp@keithp.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Keith Packard <keithp@keithp.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180203051302.9974-6-dhinakaran.pandiyan@intel.com
2018-01-08drm/tegra: dc: Properly cleanup overlay planesThierry Reding
The first overlay plane can leak if initialization of the second overlay plane fails. Fix this by properly destroying the first overlay plane on error. Suggested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-01-08drm/tegra: dc: Fix possible_crtcs mask for planesThierry Reding
Cursor and overlay planes use a possible_crtcs mask based on the DC pipe number. However, DRM requires each bit in the mask to correspond to the index of the CRTC, which will be different from the DC pipe number for a configuration where the first display controller is disabled, or where a deferred probe leads to the first display controller being probed after the first. Suggested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Implement legacy blendingThierry Reding
This implements alpha blending on legacy display controllers (Tegra20, Tegra30 and Tegra114). While it's theoretically possible to support the zpos property to enable userspace to specify the Z-order of each plane individually, this is not currently supported and the same fixed Z- order as previously defined is used. Reverts commit 71835caa00e8 ("drm/tegra: fb: Force alpha formats") since the opaque formats are now supported. Reported-by: Dmitry Osipenko <digetx@gmail.com> Fixes: 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats") Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Link DC1 to DC0 on Tegra20Dmitry Osipenko
Hardware reset isn't actually broken on Tegra20, but there is a dependency on the first display controller to be taken out of reset for the second to be enabled successfully. Model this dependency using a PM device link. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [treding@nvidia.com: minor cleanups, extend commit message] Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: Fix non-debugfs buildsArnd Bergmann
The new debugfs registration fails to build when CONFIG_DEBUGFS is disabled, because the drm_crtc structure is lacking a member in that configuration: drivers/gpu/drm/tegra/dc.c: In function 'tegra_dc_late_register': drivers/gpu/drm/tegra/dc.c:1204:28: error: 'struct drm_crtc' has no member named 'debugfs_entry' Without CONFIG_DEBUGFS, the rest of the function already degrades into nothing, so we just avoid the one assignment. Fixes: b95800eeef09 ("drm/tegra: dc: Register debugfs in ->late_register()") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: Use IOMMU groupsThierry Reding
In order to support IOMMUs more generically and transparently handle the ARM SMMU on Tegra186, move to using groups instead of devices for domain attachment. An IOMMU group is a set of devices that share the same IOMMU domain and is therefore a good match to represent what Tegra DRM needs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: Implement zpos propertyThierry Reding
Implement the standard zpos property for planes on Tegra124 and later. Earlier generations have a different blending unit that needs different programming. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Remove redundant spinlockThierry Reding
The spinlock is only used to serialize accesses to the DC_CMD_INT_MASK register. However, this register is accesses either with interrupts masked (in tegra_crtc_atomic_enable()) or protected by the vbl_lock and vblank_time_lock spinlocks of the DRM device. Therefore, these accesses don't need any extra serialization and the lock can be removed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Use direct offset to plane registersThierry Reding
Traditionally, windows were accessed indirectly, through a register selection window that required a global register to be programmed with the index of the window to access. Since the global register could be written from modesetting functions as well as the interrupt handler concurrently, accesses had to be serialized using a lock. Using direct accesses to the window registers the lock can be avoided. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-21drm/tegra: dc: Support more formatsThierry Reding
Also, split up formats into per-SoC lists because not all generations support all of them. Note that the list is now exhaustive for all RGB formats, but not for YUV and indexed formats. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: sor: Add Tegra186 supportThierry Reding
The SOR found on Tegra186 is very similar to the one found on Tegra210 and earlier. However, due to some changes in the display architecture, some programming sequences have changed and some register have moved around. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Support ARGB and ABGR formatsThierry Reding
These formats can easily be supported on all generations of Tegra. Note that the XRGB and XBGR formats that we supported were in fact using the ARGB and ABGR Tegra formats. This happened to work in cases where no alpha was being considered. This change is also a fix for those formats. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Add Tegra186 supportThierry Reding
The display architecture has changed in several signifcant ways with the new Tegra186 SoC. Display controllers are a completely different design, but have been given a frontend that simulates the register interface for earlier chips. Unfortunately the frontend isn't completely backwards compatible, so the driver needs parameterization to take the changes into account. One big change is that the total number of display controllers has been increased to three. At the same time the number of planes available has remained constant. However, planes can now be freely assigned between the display controllers, giving applications more flexibility in making the best use of the available resources. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Add Tegra186 display hub supportThierry Reding
The display architecture has changed in several significant ways with the new Tegra186 SoC. Shared between all display controllers is a set of common resources referred to as the display hub. The hub generates accesses to memory and feeds them into various composition pipelines, each of which being a window that can be assigned to arbitrary heads. Atomic state is subclassed in order to track the global bandwidth requirements and select and adjust the hub clocks appropriately. The plane code is shared to a large degree with earlier SoC generations, except where the programming differs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Move common plane code to separate fileThierry Reding
Subsequent patches will add support for Tegra186 which has a different architecture and needs different plane code but which can share a lot of code with earlier Tegra support. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Move state definition to headerThierry Reding
Move the display controller state definition to the header file so that it can be referenced by other files. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove duplicate plane funcsThierry Reding
Both tegra_overlay_plane_funcs is identical to tegra_plane_funcs. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove tegra_overlay_plane_destroy()Thierry Reding
This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove duplicate plane funcsThierry Reding
Both tegra_primary_plane_funcs and tegra_cursor_plane_funcs are identical. Get rid of the duplicate and use one set of function pointers for all planes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Remove tegra_primary_plane_destroy()Thierry Reding
This function is a simple wrapper around tegra_plane_destroy(), so it can be dropped. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Remove custom page-flip handlerThierry Reding
Tegra display hardware has GO bits and meets all the requirements to use drm_crtc_arm_vblank_event(). Use it instead and get rid of the hand- rolled implementation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: Use atomic commit helpersThierry Reding
There's no reason not to use them, and they already get all the semantics right, so rip out all of the custom code and replace it by the helpers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Support background colorThierry Reding
Starting with Tegra124, the interface to set the background color (the value generated for pixels that are not sourced from any window) is via a different register. Earlier generations called this the border color. Reverse the feature flag and assume that IP revisions that don't have support for background color will support border color instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Register debugfs in ->late_register()Thierry Reding
The ->late_register() and ->early_unregister() callbacks are called at the right time to make sure userspace only accesses interfaces when it should. Move debugfs registration and unregistration to these callback functions to avoid potential races with userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Reshuffle some codeThierry Reding
Reshuffle some code so that functions are defined closer to where they are used. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13drm/tegra: dc: Move register definitions into a tableThierry Reding
After commit 67e04d1ab19b ("drm/tegra: dc: Trace register accesses"), the debugfs register dump implementation causes excessive stack usage and can result in build warnings. To fix this, move the register definitions into a table and iterate over the table while dumping the registers to debugfs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-11-21Merge airlied/drm-next into drm-misc-nextDaniel Vetter
Bake in the conflict between the drm_print.h extraction and the addition of DRM_DEBUG_LEASES since we lost it a few too many times. Also fix a new use of drm_plane_helper_check_state in msm to follow Ville's conversion in commit a01cb8ba3f6282934cff65e89ab36b18b14cbe27 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Nov 1 22:16:19 2017 +0200 drm: Move drm_plane_helper_check_state() into drm_atomic_helper.c Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-11-20drm: Move drm_plane_helper_check_state() into drm_atomic_helper.cVille Syrjälä
drm_plane_helper_check_update() isn't a transitional helper, so let's rename it to drm_atomic_helper_check_plane_state() and move it into drm_atomic_helper.c. v2: Fix the WARNs about plane_state->crtc matching crtc_state->crtc Cc: Daniel Vetter <daniel@ffwll.ch> Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171101201619.6175-1-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-11-20drm: Check crtc_state->enable rather than crtc->enabled in ↵Ville Syrjälä
drm_plane_helper_check_state() drm_plane_helper_check_state() is supposed to do things the atomic way, so it should not be inspecting crtc->enabled. Rather we should be looking at crtc_state->enable. We have a slight complication due to drm_plane_helper_check_update() reusing drm_plane_helper_check_state() for non-atomic drivers. Thus we'll have to pass the crtc_state in manally and construct a fake crtc_state in drm_plane_helper_check_update(). v2: Fix the WARNs about plane_state->crtc matching crtc_state->crtc Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171101201558.6059-1-ville.syrjala@linux.intel.com Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2017-10-20drm/tegra: dc: Perform a complete reset sequenceThierry Reding
In order for the reset to be applied properly, the module clock must be enabled during the assertion. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20drm/tegra: dc: Make sure to set the module clock rateThierry Reding
When applying the PLL changes from the computed state object, make sure to set the rate of the display controller module clock. Failing to do so can yield to a situation where the parent will be set to the proper pixel clock, but the module clock will be divided down to the rate that is happened to be set to before the parent rate change. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-10-20drm/tegra: dc: Simplify atomic plane helper functionsThierry Reding
Remove the tegra_dc_disable_window() function whose only purpose was to allow tegra_plane_atomic_update() to also call it. Fix that by shuffling tegra_plano_atomic_disable() to before tegra_plane_atomic_update(). While at it, also remove the overlay plane helper functions because they are exactly the same as the primary plane helper functions. Signed-off-by: Thierry Reding <treding@nvidia.com>
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