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path: root/drivers/gpu/drm/nouveau/nv50_pm.c
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2012-03-13drm/nv50/hwsq: some nv92 fixesMartin Peres
The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92 This fixes some reclocking issues on my newly acquired nv92 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/pm: wait for all fifo-connected engines to idle before reclockingMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/pm: use hwsq for engine reclocking tooBen Skeggs
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/disp: more accurate function to determine active crtcsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: initial work towards proper memory reclocking, with timingsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-02-01drm/nv50/pm: signedness bug in nv50_pm_clocks_pre()Dan Carpenter
calc_mclk() returns zero on success and negative on failure but clk is a u32. v2: Martin Peres: - clk should be an int, not a u32 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: just pass gpio line to pwm_*, not entire gpio structBen Skeggs
We don't need more than the line id to determine the PWM controller, and the GPIO interfaces are about to change somewhat. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/hwsq: remove some magic, give proper opcode namesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: introduce hwsq-based memory reclockingMartin Peres
More work needs to be done on supporting the different memory types. v2 (Ben Skeggs): - fixed up conflicts from not having pausing patch first - restructured code somewhat to fit with how all the other code works - fixed bug where incorrect mpll_ctrl could get set sometimes - removed stuff that's cargo-culted from the binary driver - merged nv92+ display disable into hwsq - fixed incorrect opcode 0x5f magic at end of ucode Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: fix a typo in clock calculationMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: only touch 0x611200 on nv92-Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: stabilise transition to 100MHz mclk a bitBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: avoid touching dom6/vdec clocks if perflvl doesn't define itBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: fix thinko which lead to clocks being slightly off sometimesBen Skeggs
read_pll_ref() needs to take into account the refclk src bits in 0xc040 on some chipsets, it wasn't doing this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: 0x84/0x86 can't use "1" for nvclk src, need 0x50 methodBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: free state struct after setting clocksBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: rewrite clock management, and switch to the new pm hooksBen Skeggs
This area is horrifically complicated on these chipsets, and it's likely we will need at least a few more tweaks yet. Oh yes, and it's completely disabled on IGPs for the moment. From traces, things look potentially different there yet again. Sigh... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: convert to new fanspeed pwm controller hooksBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: mostly nailed down fan pwm frequency selectionBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: add support for pwm fan controlBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nouveau/bios: allow passing in crtc to the init table parserBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv50: improve nv50_pm_get_clock()Emil Velikov
Many of the nv50 cards have their shader and/or memory pll disabled at some stage. This patch addresses those cases, so that the function returns the correct frequency. When the shader pll is disabled, the blob reports 2*core clock Whereas for memory, the data stored in the vbios. This action is incorrect as some vbioses store a clock value that is less than the refference clock of the pll. Thus we are reporting the reff_clk as it is the frequency the pll actually operates v2 - Convert NV_INFO() messages to NV_DEBUG() Provide more information in the actuall message Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nva3: split pm backend out from nv50Ben Skeggs
This will end up quite different, it makes sense for it to be completely separate. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nouveau: run perflvl and M table scripts on mem clock changeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nouveau: pass perflvl struct to clock_pre()Ben Skeggs
On certain boards, there's BIOS scripts and memory timings that need to be modified with the memclk. Just pass in the entire perflvl struct and let the chipset-specific code decide what to do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nouveau: allow static performance level settingBen Skeggs
Guarded by a module parameter for the moment, read the code for the magic value which enables it. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-09-24drm/nv50: import initial clock get/set routines + hook up pm engineBen Skeggs
This will make nouveau_pm attempt to report the card's current performance level both during bootup, and through sysfs. This is a very initial implementation, and can be improved a *lot* Signed-off-by: Ben Skeggs <bskeggs@redhat.com>