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path: root/drivers/gpu/drm/nouveau/nouveau_drv.h
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2012-03-23drm/nve0: initial modesetting support for kepler chipsetsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: bump version to 1.0.0Ben Skeggs
The time has come to get a proper version number that we can change to indicate new features etc, rather than the lock-step 0.0.XX that we previously had. libdrm has recognised this version as compatible with 0.0.16 since 2.4.22, so hopefully any breakage people see should be very minimal. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: oops, increase channel dispc_vma to 4Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: remove m2mf creation on userspace channelsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nvc0-/disp: reimplement flip completion method as fifo methodBen Skeggs
Removes need for M2MF subchannel usage on NVC0+. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau: remove subchannel names from places where it doesn't matterBen Skeggs
These are FIFO methods, it doesn't matter what subchannel is being used. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-22drm/nouveau/ttm: always do buffer moves on kernel channelBen Skeggs
There was once good reasons for wanting the drm to be able to use M2MF etc on user channels, but they're not relevant anymore. For the general buffer move case, we've already lost by transferring between vram/sysmem already so the context switching overhead is minimal in comparison. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau: map first page of mmio early and determine chipset earlierBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: move all nv50/sor-specific code out of nouveau_dp.cBen Skeggs
Off-chip encoders (which we don't support yet anyway), and newer chipsets (such as NVD9...), will need their own code for this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/display: expose color vibrance controlChristoph Bumiller
Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50-nvc0/vm: support unsnooped system memoryBen Skeggs
v2 (Emil Velikov <emil.l.velikov@gmail.com>): - Fixed a regression on certain nv50 IGP due to not passing the correct target type to nv50_vm_addr() Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Tested-by: Johannes Obermayr <johannesobermayr@gmx.de>
2012-03-13drm/nouveau/pm: extend profile interface for destroy/init/finiBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: rework to allow selecting separate profiles for ac/batteryBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: embed timings into perflvl structsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: calculate memory timings at perflvl creation timeBen Skeggs
Statically generating the PFB register and MR values for each timing set turns out to be insufficient. There's at least one (so far) known piece of information which effects MR values which is stored in the perflvl entry on some chipsets (and in another table on later ones), which is disconnected from the timing table entries. After this change we will generate a timing set based on an input clock frequency instead, and have this data stored in the performance level data. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validationRoy Spliet
Roy Spliet: - Implement according to specs - Simplify - Make array for mc latency registers Martin Peres: - squash and split all the commits from Roy - rework following Ben Skeggs comments - add a form of timings validation - store the initial timings for later use Ben Skeggs - merge slightly modified tidy-up patch with this one - remove perflvl-dropping logic for the moment Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: improve memory timing generationRoy Spliet
- Rename several VBIOS entries to closer match the real world - Add the missing 0x100238 and 0x100240 register values - Parse bit 14 of the VBIOS timing table - "Magic value" -> tCWL, fixing some minor bugs in the process - Also name a few more by their name rather than their number. - Some values seem to be dependent on the memory type. Fix Edits by Martin Peres <martin.peres@labri.fr>: - this is a squash commit - reworked for fixing some style issues Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau: move pwm_divisor to the nouveau_pm_fan structMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: restore fan speed after suspendMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: style fixesMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50: hopefully handle the DDR2/DDR3 memtype detection somewhat betterBen Skeggs
M version 2 appears to have a table with some form of memory type info available. NVIDIA appear to ignore the table information except for this DDR2/DDR3 case (which has the same value in 0x100714). My guess is this is due to some of the supported memory types not being represented in the table. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv20-nv40: add memory type detectionBen Skeggs
NV20/NV30 is partially educated guesswork at this point, based on any information around about available memory types and a horribly unspeakable amount of vbios image scouring. I'm not entirely certain the GDDR3 define is correct, I have not spotted a single vbios with that value yet (though it is mentioned in some 1218-using nv4x vbios), but there are reports that some nv3x did use it.. NV40(100914) confirmed by switching an NV49 to DDR1/DDR2 values and making sure that the binary driver behaviour showed it had detected DDR1/DDR2 instead of GDDR3 before dying horribly. NV40(100474) confirmed by doing much the same task as above on an NV44, except this was *much* easier as changing the values didn't seem to have any noticable effect on the memory controller aside from changing the binary driver's behaviour. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv20: split PFB code out of nv10_fb.cBen Skeggs
Most functions were quite different between NV10/NV20 already, and they're about to get even more so. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau: move vram detection funcs to chipset-specific fb codeBen Skeggs
Also, display detected memory type in logs - though, we don't even try to detect this yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-01-13nouveau: Support Optimus models for vga_switcherooPeter Lekensteyn
Newer nVidia cards with Optimus do not support/use the DSM switching functions. Instead, it require a DSM function to be called prior to bringing a device into D3 state. No other _DSM calls are necessary before/after enabling/disabling a device. Switching between discrete and integrated GPU is not supported by this Optimus _DSM call, therefore return on the switching method. Signed-off-by: Peter Lekensteyn <lekensteyn@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-21drm/nouveau: Fix pushbufs over the 4GB mark.Francisco Jerez
Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/gpio: reimplement as nouveau_gpio.c, fixing a number of issuesBen Skeggs
- moves out of nouveau_bios.c and demagics the logical state definitions - simplifies chipset-specific driver interface - makes most of gpio irq handling common, will use for nv4x hpd later - api extended to allow both direct gpio access, and access using the logical function states - api extended to allow for future use of gpio extender chips - pre-nv50 was handled very badly, the main issue being that all GPIOs were being treated as output-only. - fixes nvd0 so gpio changes actually stick, magic reg needs bashing Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: just pass gpio line to pwm_*, not entire gpio structBen Skeggs
We don't need more than the line id to determine the PWM controller, and the GPIO interfaces are about to change somewhat. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/mxm: initial implementation of dcb sanitisationBen Skeggs
The DCB table provided by the VBIOS on most MXM chips has a number of entries which either need to be disabled, or modified according to the MXM-SIS Output Device Descriptors. The x86 vbios code usually takes care of this for us, however, with the large number of laptops now with switchable graphics or optimus, a lot of the time nouveau is responsible for POSTing the card instead - leaving some fun situations like, plugging in a monitor and having nouveau decide 3 connectors actually just got plugged in.. No MXM-SIS fetching methods implemented yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/i2c: do parsing of i2c-related vbios info in nouveau_i2c.cBen Skeggs
Not much point parsing the vbios data into a struct which is only used once to parse the data into another struct, go directly from vbios to nouveau_i2c_chan. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/bios: start refactoring dcb routinesBen Skeggs
This primary reason for this was mostly to avoid duplication of some of this stuff by the MXM-SIS parser. However, some other cleanups will also follow this as a result. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nvd0/disp: add support for page flippingBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: shutdown display on suspend/hibernateBen Skeggs
Known to fix some serious issues with hibernate on a couple of systems. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/disp: introduce proper init/fini, separate from create/destroyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/pm: remove the older interfaces completelyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: rewrite clock management, and switch to the new pm hooksBen Skeggs
This area is horrifically complicated on these chipsets, and it's likely we will need at least a few more tweaks yet. Oh yes, and it's completely disabled on IGPs for the moment. From traces, things look potentially different there yet again. Sigh... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/pm: make clocks_set return an error code clocks_set can fail.Martin Peres
Reporting an error is better than silently refusing to reclock. V2: Use the same logic on nv40 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: improve dithering properties, and implement proper auto modeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: add overscan compensation connector propertiesBen Skeggs
Exposes the same connector properties as the Radeon implementation, however their behaviour isn't exactly the same. The primary difference being that unless both hborder/vborder have been defined by the user, the driver will keep the aspect ratio of the overscanned area the same as the mode the display is programmed for. Enabled for digital outputs on GeForce 8 and up, excluding GF119. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau: move master modesetting init to nouveau_displayBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/hdmi: build ELD from EDID, notify audio driver of its presenceBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: s/unk05/vdec/Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/pm: remove defunct fanspeed_set/get from pm tableBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/pm: introduce generic handler for on-chip fan controllerBen Skeggs
The handling of the internal pwm fan controller is similar enough between current chipsets that it makes sense to share the logic, and bugfixes :) No hw backends converted yet, will automatically fall-through to the "old" per-chipset fanspeed hooks for now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv50/pm: mostly nailed down fan pwm frequency selectionBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/pm: manual pwm fanspeed management for nv40+ boardsMartin Peres
Exposes the following sysfs entries: - fan0_input: read the rotational speed of the fan (poll a bit during 250ms) - pwm0: set the pwm duty cycle - pwm0_min/max: set the minimum/maximum pwm value v2 (Ben Skeggs): - nv50 pwm controller code removed in favour of other more complete code - FAN_RPM -> FAN_SENSE - merged FAN_SENSE readout into common code, not at all nv50-specific - protected fanspeed changes with perflvl_wr - formatting tidying - added some comments where things are shaky v3 (Martin Peres) - ensure duty min/max from thermal table are sane Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
2011-12-21drm/nouveau/vdec: implement stub modules for the known enginesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nv40/pm: parse fan pwm divisor from vbios tablesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-20Merge tag 'v3.2-rc6' of /home/airlied/devel/kernel/linux-2.6 into drm-core-nextDave Airlie
Merge in the upstream tree to bring in the mainline fixes. Conflicts: drivers/gpu/drm/exynos/exynos_drm_fbdev.c drivers/gpu/drm/nouveau/nouveau_sgdma.c
2011-12-06drm/ttm: merge ttm_backend and ttm_tt V5Jerome Glisse
ttm_backend will only exist with a ttm_tt, and ttm_tt will only be of interest when bound to a backend. Merge them to avoid code and data duplication. V2 Rebase on top of memory accounting overhaul V3 Rebase on top of more memory accounting changes V4 Rebase on top of no memory account changes (where/when is my delorean when i need it ?) V5 make sure ttm is unbound before destroying, change commit message on suggestion from Tormod Volden Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
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