summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)Author
2021-01-26drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup
2021-01-26drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup
2021-01-26drm/i915/adl_s: Add PHYs for Alderlake SAnusha Srivatsa
2021-01-26drm/i915/adl_s: Add Interrupt SupportAnusha Srivatsa
2021-01-26drm/i915/adl_s: Add PCH supportAnusha Srivatsa
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä
2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä
2021-01-25drm/i915: Fix vblank evasion with vrrVille Syrjälä
2021-01-25drm/i915: Fix vblank timestamps with VRRVille Syrjälä
2021-01-25drm/i915: Add vrr state dumpVille Syrjälä
2021-01-25drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä
2021-01-25drm/i915/display: Add HW state readout for VRRManasi Navare
2021-01-25drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare
2021-01-25drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare
2021-01-25drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare
2021-01-25drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare
2021-01-25drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä
2021-01-25drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä
2021-01-25drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare
2021-01-25drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare
2021-01-25drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()Ville Syrjälä
2021-01-25drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä
2021-01-25drm/i915: Store framestart_delay in dev_privVille Syrjälä
2021-01-25drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup
2021-01-25drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare
2021-01-22drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada
2021-01-22drm/i915/gem: Add a helper to read data from a GEM object pageImre Deak
2021-01-22drm/i915/hdcp: Fix uninitialized symbolAnshuman Gupta
2021-01-22drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)Anshuman Gupta
2021-01-21drm/i915/dp: Don't use DPCD backlights that need PWM enable/disableLyude Paul
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä
2021-01-21drm/i915: Fix ICL MG PHY vswing handlingVille Syrjälä
2021-01-21drm/i915/dp: split out aux functionality to intel_dp_aux.cJani Nikula
2021-01-21drm/i915/dp: abstract struct intel_dp pps members to a sub-structJani Nikula
2021-01-21drm/i915/pps: move pps code over from intel_display.c and refactorJani Nikula
2021-01-21drm/i915/pps: refactor init abstractionsJani Nikula
2021-01-20drm/i915/adl_s: Add ADL-S platform info and PCI idsCaz Yokoyama
2021-01-20drm/i915/tgl: Use TGL stepping info for applying WAsAditya Swarup
2021-01-19drm/dp: Revert "drm/dp: Introduce EDID-based quirks"Lyude Paul
2021-01-19drm/i915/dp: Allow forcing specific interfaces through enable_dpcd_backlightLyude Paul
2021-01-19drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)Lyude Paul
2021-01-19drm/i915: Keep track of pwm-related backlight hooks separatelyLyude Paul
2021-01-19drm/i915: Reuse the async_flip() hook for the async flip disable w/aVille Syrjälä
2021-01-19drm/i915: Move the async_flip bit setup into the .async_flip() hookVille Syrjälä
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-21 21:37:30 +0000