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path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
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2019-03-19drm/i915: Remove the fragile array index -> link rate mappingVille Syrjälä
Rather than try to maintain some magic relationship between the link rates and the index into the wrpll params array let's just store the link rate in the array itself. Much less fragile. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-13-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Nuke icl_calc_dp_combo_pll_link()Ville Syrjälä
We already have the code to calculate the WRPLL output clock from the register values, but for some reason we're only using it for HDMI and not DP. Throw out the inflexible DP DPLL table lookup and just call the HDMI code which decodes the actual register values. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-12-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from icl_get_dpll()Ville Syrjälä
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-10-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Pass crtc_state down to icl dpll funcsVille Syrjälä
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-9-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from cnl_get_dpll()Ville Syrjälä
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-8-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Pass crtc_state down to cnl dpll funcsVille Syrjälä
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-7-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from bxt_get_dpll()Ville Syrjälä
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-6-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Pass crtc_state down to bxt dpll funcsVille Syrjälä
Simplify the calling convention of the dpll funcs by plumbing the crtc state deeper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-5-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Remove redundant on stack dpll_hw_state from skl_get_dpll()Ville Syrjälä
Just store the stuff directly into crtc_state->dpll_hw_state rather than to a temp and copying the whole thing over. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-4-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Pass crtc_state down to skl dpll funcsVille Syrjälä
Simplify the calling convention of the skl dpll funcs by plumbing the crtc state deeper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-3-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Don't pass crtc to intel_get_shared_dpll() and .get_dpll()Ville Syrjälä
Passing both crtc and its state is redundant. Pass just the state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-2-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-19drm/i915: Don't pass crtc to intel_find_shared_dpll()Ville Syrjälä
Passing both crtc and its state is redundant. Pass just the state. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207173230.22368-1-ville.syrjala@linux.intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-15drm/i915/icl: remove intel_dpll_is_combophy()Lucas De Marchi
This is only used in intel_display() and shouldn't be needed there. We don't want to keep converting from pll id to pll type so just remove the function. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190309035727.25389-6-lucas.demarchi@intel.com
2019-03-15drm/i915/icl: split combo and tbt pll funcsLucas De Marchi
Like was done for MG and combo, now finish the per-type split of the vfunc by moving TBT out of the combo functions. Now we can completely remove icl_pll_id_to_enable_reg() since each PLL type passes all the information via arguments. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190309035727.25389-5-lucas.demarchi@intel.com
2019-03-15drm/i915/icl: split combo and mg pll disableLucas De Marchi
Like was done in the enable case, split the implementation of the disable for MG and Combo PLLs. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190309035727.25389-4-lucas.demarchi@intel.com
2019-03-15drm/i915/icl: split pll enable in three stepsLucas De Marchi
Create separate functions to 1) enable power, 2) write pll config, and 3) enable pll. Doing this it makes it easier to share the functions for the different PLL types by passing the right arguments. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190309035727.25389-3-lucas.demarchi@intel.com
2019-03-15drm/i915/icl: split combo and mg pll enableLucas De Marchi
Let's start using the vfuncs to differentiate MG and Combo PLLs. The end goal is to decouple the type of the PLL from the IDs since the latter are likely to change from one platform to another. This also makes the code easier to read by not having lots of if/else chains on leaf functions. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190309035727.25389-2-lucas.demarchi@intel.com
2019-03-13drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi
This exactly same approach was already used from gen9 to gen10 and from gen10 to gen11. Let's also use it for gen11+. Let's first assume that we inherit a similar platform and than we apply the differences on top. Different from the previous attempts this will be done this time with coccinelle. We obviously need to exclude some case that is really exclusive for gen11 like PCH, Firmware, and few others. Luckly this was easy to filter by selecting the files we are touching with coccinelle as exposed below: spatch -sp_file gen11\+.cocci --in-place i915_perf.c \ intel_bios.c intel_cdclk.c intel_ddi.c \ intel_device_info.c intel_display.c intel_dpll_mgr.c \ intel_dsi_vbt.c intel_hdmi.c intel_mocs.c intel_color.c @noticelake@ expression e; @@ -!IS_ICELAKE(e) +INTEL_GEN(e) < 11 @notgen11@ expression e; @@ -!IS_GEN(e, 11) +INTEL_GEN(e) < 11 @icelake@ expression e; @@ -IS_ICELAKE(e) +INTEL_GEN(e) >= 11 @gen11@ expression e; @@ -IS_GEN(e, 11) +INTEL_GEN(e) >= 11 No functional change. v2: Remove intel_lrc.c per Tvrtko request since those were w/a for ICL hw issuea and media related configuration. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190308214300.25057-1-rodrigo.vivi@intel.com
2019-03-01drm/i915/icl: move MG pll hw_state readoutLucas De Marchi
Let the MG plls have their own hooks since it shares very little with other PLL types. It's also better so the platform info contains the info if the PLL is for MG PHY rather than relying on the PLL ids. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190222232324.16405-1-lucas.demarchi@intel.com
2019-01-31drm/i915: Pick the first unused PLL once againVille Syrjälä
commit 5b0bd14dcc6b ("drm/i915/icl: keep track of unused pll while looping") inadvertently (I presume) changed the code to pick the last unused dpll rather than the first unused one like we did before. While there should most likely be no harm in changing the order let's change back just to avoid a change in the behaviour. At least it might reduce the confusion when staring at logs (took me a while to figure out why DPLL1 being picked over DPLL0 when the latter was most definitely available). Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190130181359.20693-1-ville.syrjala@linux.intel.com Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-01-29drm/i915/icl: keep track of unused pll while loopingLucas De Marchi
Instead of looping again on the range of plls, just keep track of one unused one and use it later. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190125222444.19926-5-lucas.demarchi@intel.com
2019-01-29drm/i915/icl: use tc_port in MG_PLL macrosLucas De Marchi
Fix the TODO leftover in the code by changing the argument in MG_PLL macros. The MG_PLL ids used to access the register values can be converted from tc_port rather than port. All these registers can use the TC port to calculate the right offsets because they are only available for TC ports. The range (PORT_C onwards) may not be stable and change from platform to platform. So by using the TC id directly we avoid having to check for the platform in the "leaf functions" and thus passing dev_priv around. The helper functions were also renamed to use "tc" as prefix to make them more generic. v2: Improve commit message and fix checkpatch warning (from Paulo) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190125222444.19926-2-lucas.demarchi@intel.com
2019-01-17drm/i915/dpll_mgr: switch to kernel typesJani Nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Minor checkpatch/whitespace fixes sprinkled on top of the changed lines. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b73aefabb757acf59896bd77dbb20c2e343c6e6d.1547629303.git.jani.nikula@intel.com
2019-01-14drm/i915: Markup paired operations on display power domainsChris Wilson
The majority of runtime-pm operations are bounded and scoped within a function; these are easy to verify that the wakeref are handled correctly. We can employ the compiler to help us, and reduce the number of wakerefs tracked when debugging, by passing around cookies provided by the various rpm_get functions to their rpm_put counterpart. This makes the pairing explicit, and given the required wakeref cookie the compiler can verify that we pass an initialised value to the rpm_put (quite handy for double checking error paths). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190114142129.24398-16-chris@chris-wilson.co.uk
2018-12-03drm/i915/icl: Calculate DPLL params for DSIMadhav Chauhan
This patch calculates various DPLL dividers and parameters for DSI encoder and adjust AFE clock for DSI. For DSI, 8x clock is AFE clock. v2: Extend haswell_crtc_compute_clock() for Gen11 DSI v3: Rebase v4: use port clock instead of bitrate. v5: Reabse and remove divide by 5 v6 by Jani: - Fix indent (Madhav) - Fix dpll state calc for EDP and DP MST Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/525d41d0d893dcdc8874d2ce70afa226227ea3f4.1543500285.git.jani.nikula@intel.com
2018-10-31drm/i915/icl: Fix crash when getting DPLL of a MST encoder in TC portsJosé Roberto de Souza
enc_to_dig_port() returns NULL for encoders of type INTEL_OUTPUT_DP_MST causing the crash bellow: [ 2832.836101] BUG: unable to handle kernel paging request at 00000000000012b8 [ 2832.843062] PGD 0 P4D 0 [ 2832.845610] Oops: 0000 [#1] SMP [ 2832.848764] CPU: 2 PID: 3577 Comm: kworker/2:0 Tainted: G W 4.19.0-rc7+ #491 [ 2832.857106] Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.2352.A01.1808281852 08/28/2018 [ 2832.870734] Workqueue: events output_poll_execute [ 2832.875480] RIP: 0010:icl_get_dpll+0xa4/0x5d0 [i915] [ 2832.880449] Code: e9 03 f3 48 ab 8b 6e 74 41 8b 8c 24 5c 03 00 00 85 ed 0f 88 3f 02 00 00 83 fd 01 0f 8e ad 01 00 00 83 fd 05 0f 8f 2d 02 00 00 <83> ba b8 12 00 00 02 48 8b 36 0f 84 39 02 00 00 44 8b be ec 89 00 [ 2832.899176] RSP: 0018:ffffc90001b57a78 EFLAGS: 00010293 [ 2832.904404] RAX: 0000000000000000 RBX: ffffc90001b57a94 RCX: 0000000000083d60 [ 2832.911536] RDX: 0000000000000000 RSI: ffff8804a8c0dc00 RDI: ffffc90001b57b18 [ 2832.918668] RBP: 0000000000000003 R08: ffff8804a8c1f990 R09: ffff8804a8c1f990 [ 2832.925797] R10: 0000000000000000 R11: ffff8804a8e99600 R12: ffff8804a7760000 [ 2832.932930] R13: ffff88049e94d000 R14: ffff88049e94d000 R15: 000000000000000e [ 2832.940063] FS: 0000000000000000(0000) GS:ffff8804b0300000(0000) knlGS:0000000000000000 [ 2832.948147] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2832.953893] CR2: 00000000000012b8 CR3: 0000000004a1d004 CR4: 0000000000760ee0 [ 2832.961027] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 2832.968155] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 2832.975286] PKRU: 55555554 [ 2832.978003] Call Trace: [ 2832.980496] haswell_crtc_compute_clock+0x3d/0x68 [i915] [ 2832.985841] intel_crtc_atomic_check+0x61/0x340 [i915] [ 2832.990987] drm_atomic_helper_check_planes+0x130/0x1c0 [ 2832.996245] intel_atomic_check+0x4d5/0x10f0 [i915] [ 2833.001147] drm_atomic_check_only+0x484/0x690 [ 2833.005629] drm_atomic_commit+0x13/0x50 [ 2833.009564] restore_fbdev_mode_atomic+0x1c9/0x1e0 [ 2833.014363] drm_fb_helper_restore_fbdev_mode_unlocked+0x47/0x90 [ 2833.020368] drm_fb_helper_set_par+0x29/0x50 [ 2833.024641] drm_fb_helper_hotplug_event.part.33+0x92/0xb0 [ 2833.030130] drm_kms_helper_hotplug_event+0x26/0x30 [ 2833.035013] output_poll_execute+0x192/0x1b0 [ 2833.039293] process_one_work+0x2a5/0x5f0 [ 2833.043315] worker_thread+0x2d/0x3d0 [ 2833.046988] ? rescuer_thread+0x340/0x340 [ 2833.051009] kthread+0x112/0x130 [ 2833.054247] ? kthread_create_worker_on_cpu+0x70/0x70 [ 2833.059307] ret_from_fork+0x3a/0x50 [ 2833.062893] Modules linked in: i915 prime_numbers snd_hda_codec_realtek snd_hda_codec_generic asix snd_usb_audio snd_usbmidi_lib snd_seq_midi snd_seq_midi_event snd_rawmidi cdc_ether usbnet x86_pkg_temp_thermal xhci_pci xhci_hcd ucsi_acpi typec_ucsi typec efivarfs [last unloaded: prime_numbers] [ 2833.088917] CR2: 00000000000012b8 [ 2833.092241] ---[ end trace 25f9fe3d47af2e75 ]--- [ 2833.096895] RIP: 0010:icl_get_dpll+0xa4/0x5d0 [i915] [ 2833.101866] Code: e9 03 f3 48 ab 8b 6e 74 41 8b 8c 24 5c 03 00 00 85 ed 0f 88 3f 02 00 00 83 fd 01 0f 8e ad 01 00 00 83 fd 05 0f 8f 2d 02 00 00 <83> ba b8 12 00 00 02 48 8b 36 0f 84 39 02 00 00 44 8b be ec 89 00 [ 2833.120589] RSP: 0018:ffffc90001b57a78 EFLAGS: 00010293 [ 2833.125815] RAX: 0000000000000000 RBX: ffffc90001b57a94 RCX: 0000000000083d60 [ 2833.132946] RDX: 0000000000000000 RSI: ffff8804a8c0dc00 RDI: ffffc90001b57b18 [ 2833.140080] RBP: 0000000000000003 R08: ffff8804a8c1f990 R09: ffff8804a8c1f990 [ 2833.147213] R10: 0000000000000000 R11: ffff8804a8e99600 R12: ffff8804a7760000 [ 2833.154350] R13: ffff88049e94d000 R14: ffff88049e94d000 R15: 000000000000000e [ 2833.161483] FS: 0000000000000000(0000) GS:ffff8804b0300000(0000) knlGS:0000000000000000 [ 2833.169565] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2833.175313] CR2: 00000000000012b8 CR3: 0000000004a1d004 CR4: 0000000000760ee0 [ 2833.182449] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 2833.189578] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 2833.196712] PKRU: 55555554 MST ports are allocated from struct intel_dp_mst_encoder not from struct intel_digital_port as regular ports, so to get the TC type it is necessary check the primary digital port of the mst encoder. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181030215750.28213-5-jose.souza@intel.com
2018-10-16drm/i915/icl: Refactor icl pll functionsVandita Kulkarni
This patch adds helper function for identifying whether the given PLL is combo PHY PLL or not. This helper function is used inside various ICL functions to make them scalable. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181003072203.12848-6-mahesh1.kumar@intel.com
2018-10-16drm/i915/icl: Use helper functions to classify the portsVandita Kulkarni
Use intel_port_is_tc and intel_port_is_combophy functions to replace the individual port checks from port C to F and port A to B respectively. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181003072203.12848-5-mahesh1.kumar@intel.com
2018-10-16drm/i915/icl: Refactor get_ddi_pll using helper funcVandita Kulkarni
Use the existing port-to-id helper function, to refactor hence making it scalable. Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181003072203.12848-4-mahesh1.kumar@intel.com
2018-10-08drm/i915: Fixup kernel doc for param name changesChris Wilson
s/crtc/crtc_state/ for the kernel doc as well as the params. Fixes: 65c307fd08dd ("drm/i915: Make shared dpll functions take crtc_state, v3.") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181008104808.17457-1-chris@chris-wilson.co.uk
2018-10-05drm/i915: Make shared dpll functions take crtc_state, v3.Maarten Lankhorst
Do not rely on crtc->config any more. Remove the assertion from ibx_pch_dpll_disable, because we the dpll state tracking should already handle this case correctly. Changes since v1: - Fixup accidental early return in intel_prepare_shared_dpll, oops! Changes since v2: - Don't use the freed crtc_state in intel_crtc_disable_noatomic() Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181005095244.1324-1-maarten.lankhorst@linux.intel.com
2018-09-04drm/i915: Fix ICL+ HDMI clock readoutVille Syrjälä
Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll mgr into the clock readout function as well. v2: Refactor the code into a common function s/is_icl/gen11+/ (Rodrigo) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180903142841.14627-1-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-08-20drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as ↵Manasi Navare
separate divider value defines The register value of Divider Ratio for high speed divider (hsdiv_ratio) in MG_CLKTOP2_HSCLKCTL_PORT register is not same as the actual numerical value of the divider. So this patch implements separate divider value defines for that field. icl_mg_pll_find_divisors() can use these defines instead of magic register values. The new defines are going to be used in the next patch. v2 (from Paulo): * Rebase. * Make it look a little more like the rest of our code. v3 (from Paulo): * Make hsdiv u32 now that it's a bit field (José). Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Suggested-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180817215209.29133-1-paulo.r.zanoni@intel.com
2018-07-27drm/i915/icl: Add TBT checks for PLL calculationsAnusha Srivatsa
Add missing TBT check in the Pll calculation. v2: do not use a auxiliary function to check if status is TBT or not. (Paulo) v3: Code style changes. (Paulo) Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1532648115-29795-1-git-send-email-anusha.srivatsa@intel.com
2018-07-23Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi
We need a backmerge to get DP_DPCD_REV_14 before we push other i915 changes to dinq that could break compilation. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-07-19drm/i915/icl: compute the TBT PLL registersPaulo Zanoni
Use the hardcoded tables provided by our spec. v2: - SSC stays disabled. - Use intel_port_is_tc(). Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180711215909.23945-2-paulo.r.zanoni@intel.com
2018-07-19Merge tag 'drm-intel-next-2018-07-09' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next Higlights here goes to many PSR fixes and improvements; to the Ice lake work with power well support and begin of DSI support addition. Also there were many improvements on execlists and interrupts for minimal latency on command submission; and many fixes on selftests, mostly caught by our CI. General driver: - Clean-up on aux irq (Lucas) - Mark expected switch fall-through for dealing with static analysis tools (Gustavo) Gem: - Different fixes for GuC (Chris, Anusha, Michal) - Avoid self-relocation BIAS if no relocation (Chris) - Improve debugging cases in on EINVAL return and vma allocation (Chris) - Fixes and improvements on context destroying and freeing (Chris) - Wait for engines to idle before retiring (Chris) - Many improvements on execlists and interrupts for minimal latency on command submission (Chris) - Many fixes in selftests, specially on cases highlighted on CI (Chris) - Other fixes and improvements around GGTT (Chris) - Prevent background reaping of active objects (Chris) Display: - Parallel modeset cleanup to fix driver reset (Chris) - Get AUX power domain for DP main link (Imre) - Clean-up on PSR unused func pointers (Rodrigo) - Many PSR/PSR2 fixes and improvements (DK, Jose, Tarun) - Add a PSR1 live status (Vathsala) - Replace old drm_*_{un/reference} with put,get functions (Thomas) - FBC fixes (Maarten) - Abstract and document the usage of picking macros (Jani) - Remove unnecessary check for unsupported modifiers for NV12. (DK) - Interrupt fixes for display (Ville) - Clean up on sdvo code (Ville) - Clean up on current DSI code (Jani) - Remove support for legacy debugfs crc interface (Maarten) - Simplify get_encoder_power_domains (Imre) Icelake: - MG PLL fixes (Imre) - Add hw workaround for alpha blending (Vandita) - Add power well support (Imre) - Add Interrupt Support (Anusha) - Start to add support for DSI on Ice Lake (Madhav) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Tue 10 Jul 2018 08:41:37 AM AEST # gpg: using RSA key FA625F640EEB13CA # gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" # gpg: aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C E2A3 FA62 5F64 0EEB 13CA Link: https://patchwork.freedesktop.org/patch/msgid/20180710234349.GA16562@intel.com
2018-07-05drm/i915: Mark expected switch fall-throughsGustavo A. R. Silva
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Addresses-Coverity-ID: 141432 Addresses-Coverity-ID: 141433 Addresses-Coverity-ID: 141434 Addresses-Coverity-ID: 141435 Addresses-Coverity-ID: 141436 Addresses-Coverity-ID: 1357360 Addresses-Coverity-ID: 1357403 Addresses-Coverity-ID: 1357433 Addresses-Coverity-ID: 1392622 Addresses-Coverity-ID: 1415273 Addresses-Coverity-ID: 1435752 Addresses-Coverity-ID: 1441500 Addresses-Coverity-ID: 1454596 Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180628223541.GA17665@embeddedor.com
2018-07-02drm/i915: Use drm_plane_mask() & co.Ville Syrjälä
Use drm_{plane,crtc,encoder,connector}_mask() where appropriate. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180626194716.12522-5-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-06-21drm/i915/icl: Do read-modify-write as needed during MG PLL programmingImre Deak
Some MG PLL registers have fields that need to be preserved at their HW default or BIOS programmed values. So make sure we preserve them. v2: - Add comment to icl_mg_pll_write() explaining the need for register masks. (Vandita) - Fix patchwork checkpatch warning. v3: - Rebase on drm-tip. Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> (v1) Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180619164115.7835-1-imre.deak@intel.com
2018-06-21drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHzImre Deak
Atm we're zeroing out fields in MG_PLL_BIAS and MG_PLL_TDC_COLDST_BIAS if refclk is 38.4MHz, whereas the spec tells us to preserve them. Although the calculated values mostly match the register defaults even for the 38.4MHz case, there are some differences wrt. what BIOS programs (I noticed at least differences in the MG_PLL_BIAS/IREFTRIM and MG_PLL_BIAS/BIASCAL_EN fields). In the lack of further info on how to program these fields, just do what the spec says and preserve the BIOS state. v2: - Preserve the BIOS programmed reg fields instead of programming them. Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> (v1) Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180615143911.31082-1-imre.deak@intel.com
2018-06-14drm/i915/icl: start adding the TBT pllPaulo Zanoni
This commit just adds the register addresses and the basic skeleton of the code. The next commits will expand on more specific functions. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-15-paulo.r.zanoni@intel.com
2018-06-01drm/i915/icl: Get DDI clock for ICL based on PLLs.Manasi Navare
PLLs are the source clocks for the DDIs so in order to determine the ddi clock we need to check the PLL configuration. This gets a little tricky for ICL since there is no register bit that maps directly to the link clock. So this patch creates a separate function in intel_dpll_mgr.c to obtain the write array PLL Params and compares the set pll_params with the table to get the corresponding link clock. v2: - Fix the encoder type check (DK). - Improve our error checking, return a sane value (Mika, Paulo). - Fix table entries (Paulo). Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> [Paulo: implement v2] Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180523224444.19017-1-paulo.r.zanoni@intel.com
2018-05-07drm/i915/icl: compute the MG PLL registersPaulo Zanoni
This implements the "MG PLL Programming" sequence from our spec. The biggest problem was that the spec assumes real numbers, so we had to adjust some numbers and calculations due to the fact that the Kernel prefers to deal with integers. I recommend grabbing some coffee, a pen and paper before reviewing this patch. v2: - Correctly identify DP encoders after upstream change. - Small checkpatch issues. - Rebase. v3: - Try to impove the comment on the tdc_targetcnt calculation based on Manasi's feedback (Manasi). - Rebase. Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-7-paulo.r.zanoni@intel.com
2018-05-07drm/i915/icl: compute the combo PHY (DPLL) DP registersPaulo Zanoni
Just use the hardcoded tables provided by our spec. v2: Rebase. v3: Clarify that 38.4 uses the 19.2 table (James). Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-6-paulo.r.zanoni@intel.com
2018-05-07drm/i915/icl: compute the combo PHY (DPLL) HDMI registersPaulo Zanoni
HDMI mode DPLL programming on ICL is the same as CNL, so just reuse the CNL code. v2: - Properly detect HDMI crtcs. - Rebase after changes to the cnl function (clock * 1000). v3: - Add a comment to clarify why we treat 38.4 as 19.2 (James). Reviewed-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-5-paulo.r.zanoni@intel.com
2018-05-07drm/i915/icl: add basic support for the ICL clocksPaulo Zanoni
This commit introduces the definitions for the ICL clocks and adds the basic functions to the shared DPLL framework. It adds code for the Enable and Disable sequences for some PLLs, but it does not have the code to compute the actual PLL values, which are marked as TODO comments and should be introduced as separate commits. Special thanks to James Ausmus for investigating and fixing a bug with the placement of icl_unmap_plls_to_ports() function. v2: - Rebase around dpll_lock changes. v3: - The spec now says what the timeouts should be. - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze the machine. - Checkpatch found a white space problem. - Small adjustments before upstreaming. v4: - Move the ICL checks out of the *map_plls_to_ports() functions (James) - Add extra encoder check (James) - Call icl_unmap_plls_to_ports() later (James) v5: - Rebase after the pll struct changes. v6: - Properly make the unmap function based on encoders_post_disable() with regarding to checks and iterators. - Address checkpatch comment on "min = max = x()". Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180427231436.9353-1-paulo.r.zanoni@intel.com
2018-03-27drm/i915: reorder dpll_info membersLucas De Marchi
Remove 4-bytes hole in this struct an reorder tables accordingly. This also changes the last element of the tables to be more future-proof. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180320220637.21480-8-lucas.demarchi@intel.com
2018-03-27drm/i915: use flags from dpll_info embedded in intel_shared_dpllLucas De Marchi
Replace all users of pll->flags to use pll->info.flags. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180320220637.21480-7-lucas.demarchi@intel.com
2018-03-27drm/i915: use id from intel_shared_dpll.infoLucas De Marchi
Replace all users of pll->id to use pll->info->id. In functions using this more than once it was preferred to add an id variable to make the code easier to read. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180320220637.21480-6-lucas.demarchi@intel.com
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