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path: root/drivers/gpu/drm/amd/powerplay
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2018-02-28drm/amd/pp: Print more smu failed info on Vega10Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-28drm/amd/powerplay: fix power over limit on FijiEric Huang
power containment disabled only on Fiji and compute power profile. It violates PCIe spec and may cause power supply failed. Enabling it will fix the issue, even the fix will drop performance of some compute tests. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-02-26drm/amdgpu/powerplay/smu7: use proper dep table for mclkAlex Deucher
For mclk od, use the vdd dependency on mclk table. Looks like a cut and paste typo. Reviewed-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Move common dpm check functions to hardwaremanager.cRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Cleaning up vega10_enable_dpm_tasks functionRex Zhu
1. move display num initialize out of dpm enable tasks. 2. do not set/restore smc telemetry if dpm is runing. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Refine code in powerplay for Cz/Vega10Rex Zhu
Add dpm check functions on CZ/Vega10 to smu backend function table. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Remove dead error checking code on Vega10Rex Zhu
when smu failed, print out the error info immediately for debug. smum_send_msg_to_smu always return true, so no need to check return value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Add debug info when smu failed on Vega10Rex Zhu
When smu msssage failed, print out return value in dmesg. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Remove duplicated vega10_is_smc_ram_running callsRex Zhu
Avoid conflicts in reading the same register mmPCIE_INDEX2 with other clients Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Add a pp feature mask bit for AutoWattman featureRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/powerplay: fix thermal interrupts on vega10Eric Huang
a bug in programming thermal interrupt register masks out interrupts and driver cannot receive interrupts. Setting 0 to mask bits will fix it. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Fix bug that dpm level was not really lockedRex Zhu
Lock the dpm levels when we use SW method to modify the dpm tables directly to avoid a possible race with the smu. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-26drm/amd/pp: Fix error handling when smu return failed on Vega10.Rex Zhu
Clamp the clock index to a valid range when reading it back Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switchingAlex Deucher
The logic has moved to cgs. mclk switching with DC at higher refresh rates should work. Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <harry.wentland@amd.com>
2018-02-19drm/amd/powerplay/smu7: allow mclk switching with no displaysAlex Deucher
If there are no displays attached, there is no reason to disable mclk switching. Fixes mclks getting set to high when there are no displays attached. Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-02-19drm/amd/powerplay/vega10: allow mclk switching with no displaysAlex Deucher
If there are no displays attached, there is no reason to disable mclk switching. Fixes mclks getting set to high when there are no displays attached. Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-02-19drm/amd/powerplay: use PP_CAP macro for disable_mclk_switching_for_frame_lockAlex Deucher
Rather than open coding it. Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: remove unused headersCorentin Labbe
All thoses headers are not used by any source files. Lets just remove them. Signed-off-by: Corentin Labbe <clabbe@baylibre.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Restore power profile mode in auto dpm level on Vega10Rex Zhu
As auto power profile mode still not support on vega10, so just restore default profile mode in auto dpm level. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Expose set/get_power_limit for DGPURex Zhu
User can change power limit between [0, 1] * max power limit. Set power limit to 0, restore to max power limit. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: Remove extra pair of parenthesesMatthias Kaehlcke
The double parentheses are not needed. Removing them fixes the following warning when building with clang: drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c:419:29: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if ((data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2)) { Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: Fix enum mismatchMatthias Kaehlcke
In several locations the driver uses AMD_CG_STATE_UNGATE (type enum amd_clockgating_state) instead of AMD_PG_STATE_UNGATE (type enum amd_powergating_stat) and vice versa. Both constants have the same value, so this doesn't cause any problems, but we still want to pass the correct type. Fixing the mismatch resolves multiple warnings like this when building with clang: drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/cz_clockpowergating.c:169:7: error: implicit conversion from enumeration type 'enum amd_powergating_state' to different enumeration type 'enum amd_clockgating_state' [-Werror,-Wenum-conversion] AMD_PG_STATE_UNGATE); Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: add mmhub powergating by smu in powerplayEric Huang
new generic interface is added in powerplay. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: implement set_mmhub_powergating_by_smu for RavenEric Huang
mmhub PG is enabled by SMU FW only for Raven. Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: delete some dead codeDan Carpenter
We deleted some code in e154162ef75d ("drm/amd/powerplay: refine pp code for raven") but there were a few related bits that were missed. Let's delete them as well. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: Zero out power data in AMDGPU_PP_SENSOR_GPU_POWER readoutTom St Denis
Since 12 of the 16 bytes are not initialized with anything let's ensure they're sensibly zeroed out otherwise debugfs callers will read back garbage (because they assume debugfs wrote sensible data back...) Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Fix sysfs pp_dpm_pcie bug on CI/VIRex Zhu
when echo "01">pp_dpm_pcie the pcie dpm will fix in highest link speed. But user should expect auto speed between level 0 and level1 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Enable pp_set_power_profile_mode under manual modeRex Zhu
Only user enter manual performance mode, driver allow user configure the sclk/mclk dpm parameters through sysfs pp_power_profile_mode. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Refine pp_dpm_force_clock_level functionsRex Zhu
Only when user set manual performance mode, driver enable pp_dpm_force_clock_level. so check the mode in pp_dpm_force_clock_level, and delete the same logic in callback functions. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Delete debug info when set power_profile_modeRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm: amd: Fix trailing semicolonsLuis de Bethencourt
The trailing semicolon is an empty statement that does no operation. Removing the two instances of them since they don't do anything. Signed-off-by: Luis de Bethencourt <luisbg@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu/pp: remove the get_temperature APIAlex Deucher
This is also supported with the read_sensor API and there were no more users of the get_temperature API. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Delete unnecessary function argumentRex Zhu
in populate_single_graphic_level for smu7 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Add struct profile_mode_setting for smu7Rex Zhu
Move configurable profiling parameters to struct profile_mode_setting and initialize current_profile_setting. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Delete dead code in powerplayRex Zhu
As not support per DPM level optimization, so delete activity_target array. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Change activity_target for performance optimization on PolarisRex Zhu
And not support perDPM level optimization on Polaris, so delete sclk activity_target array. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Add update_avfs call when set_power_stateRex Zhu
when Overdrive voltage, need to disable AVFS. when OverDriv engine clock, need to recalculate AVFS voltage by disable/enable avfs feature. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Update smu7 dpm table with OD clock/voltageRex Zhu
Delete old OD type code path when populate clk. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Implement edit_dpm_table on smu7Rex Zhu
v2: - check clk against OverDrive limits from VBIOS - set OD flag when user commit the setting. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Disable OD feature on APU/IcelandRex Zhu
Not supported on APUs or Iceland. and still not enabled on CI. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Disable OD feature if VBIOS limitsRex Zhu
Check vbios to determine whether we can enable OD Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfsRex Zhu
when cat pp_od_clk_voltage it show OD_SCLK: 0: 300Mhz 800 mV 1: 466Mhz 818 mV 2: 751Mhz 824 mV 3: 1019Mhz 987 mV 4: 1074Mhz 1037 mV 5: 1126Mhz 1087 mV 6: 1169Mhz 1137 mV 7: 1206Mhz 1150 mV OD_MCLK: 0: 300Mhz 800 mV 1: 1650Mhz 1000 mV echo "s/m level clock voltage" to change sclk/mclk's clock and voltage echo "r" to restore default value. echo "c" to commit the user setting. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Add hwmgr interface for edit dpm tableRex Zhu
Add odn_edit_dpm_table function points for setting user assigned clock/voltage. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu/powerplay/vega10: fix compute profile nameAlex Deucher
COMPUTER -> COMPUTE Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: include new ip and ip offset headersHawking Zhang
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Add OD driver clock/voltage display on smu7Rex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.Rex Zhu
Add initial infrastructure for manual dpm control. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Add a new pp feature mask bit for OD featureRex Zhu
when this bit was set on module load, driver will allow the user over/under gpu clock and voltage through sysfs. by default, this bit was not set. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Move DPMTABLE_* definitions to common header fileRex Zhu
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/pp: Refine code abbreviate variable nameRex Zhu
abbreviate variable name number_of_performance_levels to num_of_pl in struct phm_odn_clock_levels Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>