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path: root/drivers/gpu/drm/amd/amdgpu
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2018-07-13drm/amdgpu: Warn and update pin_size values when destroying a pinned BOMichel Dänzer
This shouldn't happen, but if it does, we'll get a backtrace of the caller, and update the pin_size values as needed. v2: * Check bo->pin_count instead of placement flags (Christian König) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: Make pin_size values atomicMichel Dänzer
Concurrent execution of the non-atomic arithmetic could result in completely bogus values. v2: * Rebased on v2 of the previous patch Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/106872 Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: Keep track of amount of pinned CPU visible VRAMMichel Dänzer
Instead of CPU invisible VRAM. Preparation for the following, no functional change intended. v2: * Also change amdgpu_vram_mgr_bo_invisible_size to amdgpu_vram_mgr_bo_visible_size, allowing further simplification (Christian König) Cc: stable@vger.kernel.org Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/scheduler: modify args of drm_sched_entity_initNayan Deshmukh
replace run queue by a list of run queues and remove the sched arg as that is part of run queue itself Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: fix TTM move entity init orderChristian König
We are initializing the entity before the scheduler is actually initialized. This can lead to all kind of problem, but especially NULL pointer deref because of Nayan's scheduler work. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd: Use newly added interrupt source defs for SOC15.Andrey Grodzovsky
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd: Use newly added interrupt source defs for VI v3.Andrey Grodzovsky
v2: Rebase v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd/powerplay: add vega12 SMU gfxoff support v3Evan Quan
Export apis for enabling/disabling SMU gfxoff support. v2: fit the latest gfxoff support framework v3: add feature_mask control Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: reduce the idle period that RLC has to wait before request CGCGEvan Quan
Gfxoff feature may depends on the CGCG(on vega12, that's the case). This change will help to enable gfxoff feature more frequently. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDEEvan Quan
On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: drop mmRLC_PG_CNTL clear v2Evan Quan
SMU owns this register so the driver should not set it to avoid breaking gfxoff. v2: update description Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: correct rlc save restore list initialization for v2_1Evan Quan
The save restore list initialization does not have to be pg guarded. And for some asic(e.g. Vega12), it does not have cntl/gpm/srm lists. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: init CSIB regardless of rlc version and pg statusEvan Quan
CSIB init has no relation with rlc version and pg status. It should be needed regardless of them. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amdgpu: pin the csb buffer on hw init v2Evan Quan
Without this pin, the csb buffer will be filled with inconsistent data after S3 resume. And that will causes gfx hang on gfxoff exit since this csb will be executed then. v2: fit amdgpu_bo_pin change(take one less argument) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: get VCN start to process in the dpm disabled caseLeo Liu
Fixes: 22cc6c5e19 (drm/amdgpu: Add runtime VCN PG support) Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: move cache window setup after power and clock resumeLeo Liu
To make register read/write reliable Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: Take VCN jpeg ring into account in idle work handlerLeo Liu
VCN won't get power off when only jpeg active Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: Verify root PD is mapped into kernel address space (v4)Andrey Grodzovsky
Problem: When PD/PT update made by CPU root PD was not yet mapped causing page fault. Fix: Verify root PD is mapped into CPU address space. v2: Make sure that we add the root PD to the relocated list since then it's get mapped into CPU address space bt default in amdgpu_vm_update_directories. v3: Drop change to not move kernel type BOs to evicted list. v4: Remove redundant bo move to relocated list. Link: https://bugs.freedesktop.org/show_bug.cgi?id=107065 Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: Present amdgpu_task_info in VM_FAULTS.Andrey Grodzovsky
Extract and present the reposnsible process and thread when VM_FAULT happens. v2: Use getter and setter functions. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Jim Qu <Jim.Qu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: Add support for logging process info in amdgpu_vm.Andrey Grodzovsky
Add process and thread names and pids and a function to extract this info from relevant amdgpu_vm. v2: Add documentation and fix identation. v3: Add getter and setter functions for amdgpu_task_info. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Jim Qu <Jim.Qu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: Add CLK IP base offsetRex Zhu
so we can read/write the registers in CLK domain through RREG32/WREG32_SOC15 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: Reserve VM root shared fence slot for command submission (v3)Michel Dänzer
Without this, there could not be enough slots, which could trigger the BUG_ON in reservation_object_add_shared_fence. v2: * Jump to the error label instead of returning directly (Jerry Zhang) v3: * Reserve slots for command submission after VM updates (Christian König) Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/106418 Reported-by: mikhail.v.gavrilov@gmail.com Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: fix kmap error handling for bo creationsJunwei Zhang
kmap happens after bo pin, so unpin is required on error Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: allocate gart memory when it's required (v3)Junwei Zhang
Instead of calling gart address space on every bo pin, allocates it on demand v2: fix error handling v3: drop the change on amdgpu_amdkfd_gpuvm.c, not needed. Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10drm/amdgpu: separate gpu address from bo pinJunwei Zhang
It could be got by amdgpu_bo_gpu_offset() if need Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next More features for 4.19: - Use core pcie functionality rather than duplicating our own for pcie gens and lanes - Scheduler function naming cleanups - More documentation - Reworked DC/Powerplay interfaces to improve power savings - Initial stutter mode support for RV (power feature) - Vega12 powerplay updates - GFXOFF fixes - Misc fixes Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180705221447.2807-1-alexander.deucher@amd.com
2018-07-06Merge tag 'drm-misc-next-2018-07-04' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 4.19: UAPI Changes: v3d: add fourcc modicfier for fourcc for the Broadcom UIF format (Eric Anholt) Cross-subsystem Changes: console/fbcon: Add support for deferred console takeover (Hans de Goede) Core Changes: dma-fence clean up, improvements and docs (Daniel Vetter) add mask function for crtc, plane, encoder and connector DRM objects(Ville Syrjälä) Driver Changes: pl111: add Nomadik LCDC variant (Linus Walleij) Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180704234641.GA3981@juma
2018-07-05drm/amdgpu: update documentation for amdgpu_drv.cSonny Jiang
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd: Remove errors from sphinx documentationDarren Powell
Eliminating the warnings produced by sphinx when processing the sphinx comments in amdgpu_device.c & amdgpu_mn.c Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: use pcie functions for link width and speedAlex Deucher
Use the newly exported pci functions to get the link width and speed rather than using the drm duplicated versions. Also query the GPU link caps directly rather than hardcoding them. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: switch firmware path for SI partsAlex Deucher
Use separate firmware path for amdgpu to avoid conflicts with radeon on SI parts. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: switch firmware path for CIK parts (v2)Alex Deucher
Use separate firmware path for amdgpu to avoid conflicts with radeon on CIK parts. v2: squash in logic simplification (Alex) Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: fix user fence write race conditionNicolai Hähnle
The buffer object backing the user fence is reserved using the non-user fence, i.e., as soon as the non-user fence is signaled, the user fence buffer object can be moved or even destroyed. Therefore, emit the user fence first. Both fences have the same cache invalidation behavior, so this should have no user-visible effect. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: update uvd_v6_0_ring_vm_funcs to use new nop packetAlex Deucher
Was missed when updating the uvd 6 module. Fixes: 1aac3c9180 (drm/amdgpu: fix insert nop for UVD6 ring) Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-07-05drm/amdgpu: fix the wrong type of gem object creationHuang Rui
We still use legacy type of gem_object_create, it should update to ttm_bo_type now. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd: add SPDX identifier and clarify licenseDirk Hohndel (VMware)
This is dual licensed under GPL-2.0 or MIT. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Dirk Hohndel (VMware) <dirk@hohndel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd: Replace drm_dev_unref with drm_dev_putThomas Zimmermann
This patch unifies the naming of DRM functions for reference counting of struct drm_device. The resulting code is more aligned with the rest of the Linux kernel interfaces. Signed-off-by: Thomas Zimmermann <contact@tzimmermann.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu/vce: simplify vce instance setupAlex Deucher
Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu/sdma: simplify sdma instance setupAlex Deucher
Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu/pm: fix display count in non-DC pathAlex Deucher
new_active_crtcs is a bitmask, new_active_crtc_count is the actual count. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: fix swapped emit_ib_size in vce3Alex Deucher
The phys and vm versions had the values swapped. Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Remove amdgpu_gem_map_attach target_dev documentationMichel Dänzer
The parameter was removed. Fixes: a19741e5e5a9 "dma_buf: remove device parameter from attach callback v2" Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Add AMDGPU_GPU_PAGES_IN_CPU_PAGE defineMichel Dänzer
To hopefully make the code dealing with GPU vs CPU pages a little clearer. Suggested-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Use gmc_vram_full_visible in vram_mgr_bo_invisible_sizeMichel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Dynamically probe for ATIF handle (v2)Lyude Paul
The other day I was testing one of the HP laptops at my office with an i915/amdgpu hybrid setup and noticed that hotplugging was non-functional on almost all of the display outputs. I eventually discovered that all of the external outputs were connected to the amdgpu device instead of i915, and that the hotplugs weren't being detected so long as the GPU was in runtime suspend. After some talking with folks at AMD, I learned that amdgpu is actually supposed to support hotplug detection in runtime suspend so long as the OEM has implemented it properly in the firmware. On this HP ZBook 15 G4 (the machine in question), amdgpu wasn't managing to find the ATIF handle at all despite the fact that I could see acpi events being sent in response to any hotplugging. After going through dumps of the firmware, I discovered that this machine did in fact support ATIF, but that it's ATIF method lived in an entirely different namespace than this device's handle (the device handle was \_SB_.PCI0.PEG0.PEGP, but ATIF lives in ATPX's handle at \_SB_.PCI0.GFX0). So, fix this by probing ATPX's ACPI parent's namespace if we can't find ATIF elsewhere, along with storing a pointer to the proper handle to use for ATIF and using that instead of the device's handle. This fixes HPD detection while in runtime suspend for this ZBook! v2: Update the comment to reflect how the namespaces are arranged based on the system configuration. (Alex) Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Add amdgpu_atpx_get_dhandle()Lyude Paul
Since it seems that some vendors are storing the ATIF ACPI methods under the same handle that ATPX lives under instead of the device's own handle, we're going to need to be able to retrieve this handle later so we can probe for ATIF there. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: s/disp_detetion_ports/disp_detection_ports/Lyude Paul
Fix typo. Reviewed-by: Jim Qu <Jim.Qu@amd.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Make struct amdgpu_atif private to amdgpu_acpi.cLyude Paul
Currently, there is nothing in amdgpu that actually uses these structs other than amdgpu_acpi.c. Additionally, since we're about to start saving the correct ACPI handle to use for calling ATIF in this struct this saves us from having to handle making sure that the acpi_handle (and by proxy, the type definition for acpi_handle and all of the other acpi headers) doesn't need to be included within the amdgpu_drv struct itself. This follows the example set by amdgpu_atpx_handler.c. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Add stutter mode ctrl in module parameterrex zhu
Enable stutter mode can save power in low DRAM use cases including but not limited to productivity application use, web browsing, and video playback. Currently this feature is disabled by default. Make bit 17 in module parameter amdgpu_pp_feature_mask as stutter mode mask, so user can enable/disable this feature easily. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: Move CG/PG setting out of delay worker threadRex Zhu
Partially revert commit 2dc80b00652f ("drm/amdgpu: optimize amdgpu driver load & resume time")' 1. CG/PG enablement are part of gpu hw ip initialize, we should wait for them complete. otherwise, there are some potential conflicts, for example, Suspend and CG enablement concurrently. 2. better run ib test after hw initialize completely. That is to say, ib test should be after CG/PG enablement. otherwise, the test will not cover the cg/pg/poweroff enable case. Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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