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path: root/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
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2018-09-26drm/amdgpu: move more defines into amdgpu_irq.hChristian König
Everything that isn't related to the IH ring. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-08-13drm/amdgpu/uvd: UVD entity initialization relys on ring initializationEmily Deng
Entity init should after ring init, as the entity's sched_rq's initialization is in ring init. SWDEV-161495 Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13drm/amd: Use newly added interrupt source defs for VI v3.Andrey Grodzovsky
v2: Rebase v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18drm/amdgpu: fix insert nop for UVD5 ringLeo Liu
NO_OP register should be writen to 0 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18drm/amdgpu/vg20:Restruct uvd to support multiple uvdsJames Zhu
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: remove now superflous *_hdp operationChristian König
All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-27drm/amdgpu: rename vm_id to vmidChristian König
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/amdgpu: fix UVD mc offsetsPiotr Redlewski
When UVD bo is created, its size is based on the information from firmware header (ucode_size_bytes). The same value should be be used when programming UVD mc controller offsets, otherwise it can happen that (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will point AMDGPU_GPU_PAGE_SIZE bytes after the UVD bo end. Second issue is that when programming the mmUVD_VCPU_CACHE_SIZE0 register, AMDGPU_UVD_FIRMWARE_OFFSET should be taken into account. If it isn't, (mmUVD_VCPU_CACHE_OFFSET2 + mmUVD_VCPU_CACHE_SIZE2) will always point AMDGPU_UVD_FIRMWARE_OFFSET bytes after the UVD bo end. v2: move firmware size calculation into macro definition v3: align firmware size to the gpu page size Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Piotr Redlewski <predlewski@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-04drm/amdgpu: change redundant init logs to debug levelpding
When this VF stays in exclusive mode for long, other VFs will be impacted. The redundant messages causes exclusive mode timeout when they're redirected. That is a normal use case for cloud service to redirect guest log to virtual serial port. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: pding <Pixel.Ding@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-04drm/amdgpu: various cleanups for uvd/vce.Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu: switch ih handling to two levels (v3)Alex Deucher
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu: change wptr to 64 bits (v2)Ken Wang
Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-13drm/amdgpu: read hw register to check pg status.Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-02-08drm/amdgpu: refine uvd5.0/6.0 code.Rex Zhu
1. delete redundant cg pg mask check. pg mask use to ctrl power on/down uvd. not start/stop uvd. cg mask will be check when enable mgcg. 2. no need to start uvd when initializ. when ring test/ib test/encode, uvd was enabled. when uvd idle, uvd was stopped. 3. chang cg pg sequence in powerplay. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-27drm/amdgpu: add get clockgating_state method for uvd v5&v6Huang Rui
Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-01-06drm/amdgpu: remove static integer for uvd pp stateYintian Tao
At two gpu core condition, static integer will cause that second gpu core uvd state setting will be directly skipped due to the first one setting Signed-off-by: Yintian Tao <yttao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-12-06drm/amdgpu: fix bug mclk can't change on PolarisRex Zhu
the root cause is we gate the clock to uvd vcpu. mclk's change should need the response from uvd if it is power on. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-11drm/amdgpu: refine uvd 5.0 clock gate feature.Rex Zhu
1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-11-11drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-27drm/amdgpu: enable uvd bypass mode for CI/VI.Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: rework IP block registration (v2)Alex Deucher
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: move align_mask and nop into ring funcs as well (v2)Christian König
They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: move the ring type into the funcs structure (v2)Christian König
It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode ring structures as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-10-25drm/amdgpu: move IB and frame size directly into the engine descriptionChristian König
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-09-16drm/amdgpu/uvd5: add ring callbacks for ib and dma frame sizeAlex Deucher
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-08-24drm/amdgpu: switch UVD code to use UVD_NO_OP for paddingAlex Deucher
Replace packet2's with packet0 writes to UVD_NO_OP. The value written to UVD_NO_OP does not matter. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-29drm/amdgpu: move UVD IB test into common code v2Christian König
Since we now raise the clocks from begin_use() we don't need a separate function for each hw generation any more. v2: remove unintentional lowering of the UVD clocks, fix typos for CIK hw. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-29drm/amdgpu: use begin/end_use for UVD power/clock gatingChristian König
This fixes turning power and clock on when it is actually needed. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-07-07drm/amdgpu: implement HDP functions for UVD v2Christian König
Flush and invalidate the HDP caches. v2: fix typo in comment Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: move VM fields into jobChristian König
They are the same for all IBs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amdgpu: move context switch handling into common code v2Christian König
It was a source of bugs to repeat that in each IP version. v2: rename parameter Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-11drm/amd/amdgpu: Add name field to amd_ip_funcs (v2)Tom St Denis
Add name that we can print out in kernel messages to aid in debugging. v2: drop DAL changes for upstream Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amd/amdgpu: Drop print_status callbacks.Tom St Denis
First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: use max_dw in ring_initChristian König
Instead of specifying the total ring size calculate that from the maximum number of dw a submission can have and the number of concurrent submissions. This fixes UVD with 8 concurrent submissions or more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-04drm/amdgpu: handle more than 10 UVD sessions (v2)Arindam Nath
Change History -------------- v2: - Make firmware version check correctly. Firmware versions >= 1.80 should all support 40 UVD instances. - Replace AMDGPU_MAX_UVD_HANDLES with max_handles variable. v1: - The firmware can handle upto 40 UVD sessions. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Ayyappa Chandolu <ayyappa.chandolu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-02drm/amd/amdgpu: Add SW clock gating support to UVD 5 and 6Tom St Denis
This patch adds support for software clock gating to UVD 5 and UVD 6 blocks with a preliminary commented out hardware gating routine. Currently hardware gating does not work so it's not activated. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-04-04drm/amdgpu: save and restore UVD context with suspend and resumeLeo Liu
and revert fix following it accordingly Revert "drm/amdgpu: stop trying to suspend UVD sessions v2" Revert "drm/amdgpu: fix the UVD suspend sequence order" Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-14Merge drm-fixes into drm-next.Dave Airlie
Nouveau wanted this to avoid some worse conflicts when I merge that.
2016-02-12drm/amdgpu/vi: move uvd tiling config setup into uvd codeAlex Deucher
Split uvd and gfx programming. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amdgpu: send UVD IB tests directly to the ring againChristian König
We need the IB test for GPU resets as well and the scheduler should be stoped then. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amdgpu: make pad_ib a ring function v3Christian König
The padding depends on the firmware version and we need that for BO moves as well, not only for VM updates. v2: new approach of making pad_ib a ring function v3: fix typo in macro name Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amdgpu: remove the ring lock v2Christian König
It's not needed any more because all access goes through the scheduler now. v2: Update commit message. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amdgpu: remove some more semaphore leftoversAlex Deucher
No longer needed since semaphores were removed. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-10drm/amdgpu: clean up hw semaphore support in driverChunming Zhou
No longer used. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08drma/dmgpu: move cg and pg flags into shared headersAlex Deucher
So they can be used by powerplay. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08drm/amdgpu: be consistent with uvd cg flagsAlex Deucher
Don't do anything if the uvd cg flags are not set. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-02-08drm/amdgpu: handle uvd pg flags properlyAlex Deucher
Don't attempt to start/stop the uvd block if pg is disabled. Reviewed-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-10-21drm/amdgpu: remove old lockup detection infrastructureChristian König
It didn't worked to well anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
2015-09-23drm/amdgpu: fix the UVD suspend sequence orderLeo Liu
Fixes suspend issues with UVD. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-09-02drm/amdgpu: add insert_nop ring func and default implementationJammy Zhou
The insert_nop function is added to amdgpu_ring_funcs structure as well as the default implementation Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
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