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Currently we already have two pin configuration related callbacks
available for GPIO chips .set_single_ended() and .set_debounce(). In
future we expect to have even more, which does not scale well if we need
to add yet another callback to the GPIO chip structure for each possible
configuration parameter.
Better solution is to reuse what we already have available in the
generic pinconf.
To support this, we introduce a new .set_config() callback for GPIO
chips. The callback takes a single packed pin configuration value as
parameter. This can then be extended easily beyond what is currently
supported by just adding new types to the generic pinconf enum.
If the GPIO driver is backed up by a pinctrl driver the GPIO driver can
just assign gpiochip_generic_config() (introduced in this patch) to
.set_config and that will take care configuration requests are directed
to the pinctrl driver.
We then convert the existing drivers over .set_config() and finally
remove the .set_single_ended() and .set_debounce() callbacks.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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gpiochip_add_data is already used to add data pointer and chip.
Lets rely on gpiochip_get_data which is getting used in other
gpio_chip functions.
Signed-off-by: Amitesh Singh <singh.amitesh@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Avoids gpiolib assumptions on initial pin direction, allowing user to observe
power-on settings.
Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Fix a typo causing a build regression.
Fixes: f90c6bdb690b ("gpio: f7188x: use the new open drain callback")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The F7188x chips supports setting the pins in open drain mode.
Activate the new .set_single_ended() callback.
Cc: Peter Hung <hpeter@gmail.com>
Cc: Andreas Bofjall <andreas@gazonk.org>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Align to how we handle bitmasks in most drivers in the
subsystem: using the BIT(n) macro over (1 << n).
Cc: Peter Hung <hpeter@gmail.com>
Cc: Andreas Bofjall <andreas@gazonk.org>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use devm_gpiochip_add_data() for GPIO registration and remove the
need of driver callback .remove.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
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Add F81866 GPIO supports
Fintek F81866 is a SuperIO. It contains HWMON/GPIO/Serial Ports.
and it has totally 72(9x8 sets) gpio pins.
Here is the PDF spec:
http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html
The control method is the same with F7188x, but we should care the address
of GPIO8x.
GPIO address is below:
GPIO0x based: 0xf0
GPIO1x based: 0xe0
GPIO2x based: 0xd0
GPIO3x based: 0xc0
GPIO4x based: 0xb0
GPIO5x based: 0xa0
GPIO6x based: 0x90
GPIO7x based: 0x80
GPIO8x based: 0x88 <-- not 0x70.
Signed-off-by: Peter Hung <hpeter+linux_kernel@gmail.com>
Acked-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This makes the driver use the data pointer added to the gpio_chip
to store a pointer to the state container instead of relying on
container_of().
Cc: Andreas Bofjall <andreas@gazonk.org>
Cc: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use the wrapper function for retrieving the platform data instead of
accessing dev->platform_data directly.
Signed-off-by: Nizam Haider <nijamh@cdac.in>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The name .dev in a struct is normally reserved for a struct device
that is let us say a superclass to the thing described by the struct.
struct gpio_chip stands out by confusingly using a struct device *dev
to point to the parent device (such as a platform_device) that
represents the hardware. As we want to give gpio_chip:s real devices,
this is not working. We need to rename this member to parent.
This was done by two coccinelle scripts, I guess it is possible to
combine them into one, but I don't know such stuff. They look like
this:
@@
struct gpio_chip *var;
@@
-var->dev
+var->parent
and:
@@
struct gpio_chip var;
@@
-var.dev
+var.parent
and:
@@
struct bgpio_chip *var;
@@
-var->gc.dev
+var->gc.parent
Plus a few instances of bgpio that I couldn't figure out how
to teach Coccinelle to rewrite.
This patch hits all over the place, but I *strongly* prefer this
solution to any piecemal approaches that just exercise patch
mechanics all over the place. It mainly hits drivers/gpio and
drivers/pinctrl which is my own backyard anyway.
Cc: Haavard Skinnemoen <hskinnemoen@gmail.com>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: Alek Du <alek.du@intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Jiri Kosina <jkosina@suse.cz>
Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no>
Acked-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch fixes some issues given by checkpatch. Fixes include
bracket placement, spacing and indenting.
Signed-off-by: Daniel Lockyer <thisisdaniellockyer@gmail.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for the GPIOs found on the Fintek SuperI/O chip F71869A,
such as the one found on the Jetway JNF99-525 motherboard, to the f7188x
gpio driver.
Signed-off-by: Andreas Bofjall <andreas@gazonk.org>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for the GPIOs found on the Fintek SuperI/O chip F71869, such
as the one found on the Jetway NF96u-525 motherboard, to the f7188x gpio
driver.
Signed-off-by: Andreas Bofjall <andreas@gazonk.org>
Tested-by: Les Schaffer <schaffer@optonline.net>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The company is called "Fintek", not "Fintech". Fix it.
Signed-off-by: Andreas Bofjall <andreas@gazonk.org>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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A platform_driver does not need to set an owner, it will be populated by the
driver core.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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Signed-off-by: abdoulaye berthe <berthe.ab@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Since request_muxed_region() is used to synchronize access on the
Super-I/O controller, then the can_sleep attribute must be set for
the f7188x GPIO chips.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch adds support for the GPIOs found on the Fintek super-I/O
chips F71882FG and F71889F.
A super-I/O is a legacy I/O controller embedded on x86 motherboards. It
is used to connect the low-bandwidth devices. Among others functions the
F71882FG/F71889F provides: a parallel port, two serial ports, a keyboard
controller, an hardware monitoring controller and some GPIO pins.
Note that this super-I/Os are embedded on some Atom-based LaCie NASes.
The GPIOs are used to control the LEDs and the hard drive power.
Changes since v3:
- Use request_muxed_region to protect the I/O ports against concurrent
accesses.
Changes since v2:
- Remove useless NULL setters for driver data.
Changes since v1:
- Enhance the commit message by describing what is a Super-I/O.
- Use self-explanatory names for the GPIO register macros.
- Add a comment to explain the platform device and driver registration.
- Fix gpio_get when GPIO is configured in input mode. I only had
the hardware to check this mode recently...
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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