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path: root/drivers/dma/xilinx
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2018-01-08dmaengine: xilinx_dma: Free BD consistent memoryKedareswara rao Appana
Free BD consistent memory while freeing the channel i.e in free_chan_resources. Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2018-01-08dmaengine: xilinx_dma: Fix warning variable prev set but not usedKedareswara rao Appana
This patch fixes the below sparse warning in the driver drivers/dma/xilinx/xilinx_dma.c: In function ‘xilinx_vdma_dma_prep_interleaved’: drivers/dma/xilinx/xilinx_dma.c:1614:43: warning: variable ‘prev’ set but not used [-Wunused-but-set-variable] struct xilinx_vdma_tx_segment *segment, *prev = NULL; Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2018-01-08dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdmaKedareswara rao Appana
If the hardware is configured for Scatter Gather(SG) mode, and hardware is idle, in the control register SG mode bit must be set to a 0 then back to 1 by the software, to force the CDMA SG engine to use a new value written to the CURDESC_PNTR register, failure to do so could result errors from the dmaengine. This patch updates the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Fix typosVinod Koul
some typos is comments, so fix them up /s/enusres/ensures /s/descripotrs/descriptors /s/Submited/Submitted /s/pollling/polling Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Differentiate probe based on the ip typeKedareswara rao Appana
This patch updates the probe banner info based on the ip probed. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: fix style issues from checkpatchKedareswara rao Appana
This patch fixes below. ERROR: open brace '{' following function definitions go on the next line +static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, + struct device_node *node) { Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Fix kernel doc warningsKedareswara rao Appana
This patch fixes the kernel doc warnings in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Fix race condition in the driver for multiple ↵Kedareswara rao Appana
descriptor scenario As per axi dmaengine spec the software must not move the tail pointer to a location that has not been updated (next descriptor field of the h/w descriptor should always point to a valid address). When user submits multiple descriptors on the recv side, with the current driver flow the last buffer descriptor next descriptor field points to a invalid location, resulting the invalid data or errors from the axidma dmaengine. This patch fixes this issue by creating a buffer descritpor chain during channel allocation itself and use those buffer descriptors for the subsequent dma operations. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdmaKedareswara rao Appana
VDMA engine default frame buffer configuration is cirular mode. in this mode dmaengine continuously circles through h/w configured fstore frame buffers. When vdma h/w is configured for more than one frame. for example h/w is configured for n number of frames, user submits less than n number of frames and triggered the dmaengine using issue_pending API. since the h/w (or) driver default configuraiton is circular mode h/w tries to write/read from an invalid frame buffer resulting errors from the vdma dmaengine. This patch fixes this issue by enabling the park mode as default mode configuration for frame buffers in s/w, so that driver can handle all cases for "k" frames where n%k==0 (n is a multiple of k) by simply replicating the frame pointers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: xilinx_dma: Check for channel idle state before submitting dma ↵Kedareswara rao Appana
descriptor Add variable for checking channel idle state to ensure that dma descriptor is not submitted when dmaengine is in progress. This will avoid the polling for a bit in the status register to know dma state in the driver hot path. Reviewed-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix race condition in the probeKedareswara rao Appana
Incase of interrupt property is not present, Driver is trying to free an invalid irq, This patch fixes it by adding a check before freeing the irq. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix issues with overflow interruptKedareswara rao Appana
This patch fixes the below issues. --> Need to clear the channel data count register when overflow interrupts occurs. --> Reduce the log level from _info to _dbg when overflow interrupt occurs. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix warning variable 'val' set but not usedKedareswara rao Appana
This patch fixes the below warning drivers/dma/xilinx/zynqmp_dma.c: In function 'zynqmp_dma_handle_ovfl_int': drivers/dma/xilinx/zynqmp_dma.c:522:6: warning: variable 'val' set but not used [-Wunused-but-set-variable] Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Fix kernel doc-formatKedareswara rao Appana
This patch fixes the below kernel doc warnings drivers/dma/xilinx/zynqmp_dma.c:552: info: Scanning doc for zynqmp_dma_device_config drivers/dma/xilinx/zynqmp_dma.c:558: warning: No description found for return value of 'zynqmp_dma_device_config' drivers/dma/xilinx/zynqmp_dma.c:649: info: Scanning doc for zynqmp_dma_free_descriptors drivers/dma/xilinx/zynqmp_dma.c:653: warning: No description found for parameter 'chan' drivers/dma/xilinx/zynqmp_dma.c:653: warning: Excess function parameter 'dchan' description in 'zynqmp_dma_free_descriptors' Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-18dmaengine: zynqmp_dma: Add runtime pm supportKedareswara rao Appana
This patch adds runtime pm support in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-17dmaengine: xilinx_dma: Move enum xdma_ip_type to driver fileLars-Peter Clausen
The enum xdma_ip_type is only used inside the Xilinx DMA driver and not exported to any consumers (nor should it be). So move it from the global header to driver file itself. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-09-06Merge branch 'topic/dmatest' into for-linusVinod Koul
2017-09-05dmaengine: xilinx_dma: Fix error code format specifierLars-Peter Clausen
'err' is a signed int and error codes are typically negative numbers, so use '%d' instead of '%u' to format the error code in the error message. Fixes: ba16db36b5dd ("dmaengine: vdma: Add clock support") Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-08-22dmaengine: remove DMA_SG as it is dead code in kernelDave Jiang
There are no in kernel consumers for DMA_SG op. Removing operation, dead code, and test code in dmatest. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Gary Hook <gary.hook@amd.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Li Yang <leoyang.li@nxp.com> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-07-03dmaengine: zynqmp_dma: Remove max len check in zynqmp_dma_prep_memcpyStefan Roese
Remove check for "len > ZYNQMP_DMA_MAX_TRANS_LEN" as its not needed. If the length is larger, the transfer is split up into multiple parts with the max descriptor length already. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kedareswara rao Appana <appanad@xilinx.com> Cc: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-03-14dmaengine: xilinx: avoid memory corruption for device_prep_dma_memcpy()Akinobu Mita
The device_prep_dma_memcpy() callback for this driver allocates a new xilinx_dma_tx_descriptor whose TX segments list is initialized as empty, but then gets invalid TX segment pointer by list_last_entry() from the empty TX segments list and memory corruption happens by the attempt to update the next descriptor in invalid TX segment pointer. This removes unnecessary memory access for nonexistent tail TX segment which causes memory corruption. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-03-14dmaengine: xilinx: fix device_terminate_all() callback for AXI CDMAAkinobu Mita
The device_terminate_all() callback for this driver stops current DMA operations by clearing RUNSTOP bit in the control register and waiting HALTED bit set in the status register. But AXI CDMA which is one of the supported DMA engine by this driver does not provide the run / stop controls and those bits in the control and status registers are reserved. So when device_terminate_all() is called, the error message is printed and the channel is marked as having errors in xilinx_dma_halt(). This change adds stop_transfer() callback which differentiates CDMA and other DMA engine. The CDMA's one avoids the unsupported operations and instead polls the status register to check if the DMA operations are in progress for AXI CDMA. Cc: Vinod Koul <vinod.koul@intel.com> Cc: Kedareswara rao Appana <appana.durga.rao@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-08-08dmengine: xilinx_dma: convert callback to helper functionVinod Koul
Move the xilinx driver to new dmaengine callback Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-24dmaengine: zynqmp_dma: add missing MODULE_LICENSEArnd Bergmann
We get a warning about the missing MODULE_LICENSE tag for this newly added driver module: WARNING: modpost: missing MODULE_LICENSE() in drivers/dma/xilinx/zynqmp_dma.o see include/linux/module.h for more information This adds a "GPL" license, matching the "version 2 or later" information in the comment at the start of the file. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-24dmaengine: zynqmp_dma: Fix static checker warningKedareswara rao Appana
This patch fixes the below static checker warning drivers/dma/xilinx/zynqmp_dma.c:973 zynqmp_dma_chan_probe() warn: was && intended here instead of ||? Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-12dmaengine: zynqmp: avoid cast warningArnd Bergmann
The newly added zynqmp_dma driver produces a warning on 32-bit architectures when dma_addr_t is 64-bit wide: drivers/dma/xilinx/zynqmp_dma.c: In function 'zynqmp_dma_config_sg_ll_desc': drivers/dma/xilinx/zynqmp_dma.c:321:9: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v); ^ drivers/dma/xilinx/zynqmp_dma.c:321:29: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] ((dma_addr_t)sdesc - (dma_addr_t)chan->desc_pool_v); This changes the cast to the more appropriate uintptr_t. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-12dmaengine: xilinx: Fix race condition in axi dma cyclic dma modeKedareswara rao Appana
In cyclic DMA mode need to link the tail bd segment with the head bd segment to process bd's in cyclic. Current driver is doing this only for tx channel needs to update the same for rx channel case also. This patch fixes the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: Add Xilinx zynqmp dma engine driver supportKedareswara rao Appana
Added the driver for zynqmp dma engine used in Zynq UltraScale+ MPSoC. This dma controller supports memory to memory and I/O to I/O buffer transfers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: xilinx: Use different channel names for each dmaKedareswara rao Appana
Current driver assumes that child node channel name is either "xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel" which is confusing the users of AXI DMA and CDMA. This patch fixes this issue by using different channel names for the AXI DMA and AXI CDMA child nodes. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: xilinx: Rename driver and configKedareswara rao Appana
In the existing vdma driver support for AXI DMA and CDMA got added so the driver is no longer VDMA specific. This patch renames the driver and DT binding doc to xilinx_dma and updates the Kconfig description for all the DMAS. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-07-08dmaengine: vdma: Add support for mulit-channel dma modeKedareswara rao Appana
This patch adds support for AXI DMA multi-channel dma mode Multichannel mode enables DMA to connect to multiple masters and slaves on the streaming side. In Multichannel mode AXI DMA supports 2D transfers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-21dmaengine: vdma: Add 64 bit addressing support for the axi cdmaKedareswara rao Appana
The AXI CDMA is a soft ip, which can be programmed to support 32 bit addressing or greater than 32 bit addressing. When the AXI CDMA ip is configured for 32 bit address space in simple dma mode the source/destination buffer address is specified by a single register(18h for Source buffer address and 20h for Destination buffer address). When configured in SG mode the current descriptor and tail descriptor are specified by a Single register(08h for curdesc 10h for tail desc). When the AXI CDMA core is configured for an address space greater than 32 then each buffer address or descriptor address is specified by a combination of two registers. The first register specifies the LSB 32 bits of address, while the next register specifies the MSB 32 bits of address. For example, 08h will specify the LSB 32 bits while 0Ch will specify the MSB 32 bits of the first start address. So we need to program two registers at a time. This patch adds the 64 bit addressing support to the axicdma IP in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-21dmaengine: vdma: Add 64 bit addressing support for the axi dmaKedareswara rao Appana
The AXI DMA is a soft ip, which can be programmed to support 32 bit addressing or greater than 32 bit addressing. When the AXI DMA ip is configured for 32 bit address space in simple dma mode the buffer address is specified by a single register (18h for MM2S channel and 48h for S2MM channel). When configured in SG mode The current descriptor and tail descriptor are specified by a single Register(08h for curdesc 10h for tail desc for MM2S channel and 38h for Curdesc and 40h for tail desc for S2MM). When the AXI DMA core is configured for an address space greater than 32 then each buffer address or descriptor address is specified by a combination of two registers. The first register specifies the LSB 32 bits of address, while the next register specifies the MSB 32 bits of address. For example, 48h will specify the LSB 32 bits while 4Ch will specify the MSB 32 bits of the first start address. So we need to program two registers at a time. This patch adds the 64 bit addressing support for the axidma IP in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-13dmaengine: xilinx-vdma: add some sanity checksArnd Bergmann
The newly added xilinx_dma_prep_dma_cyclic function sometimes causes a gcc warning about the use of the segment function in case we never run into the inner loop of the function: dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic': dma/xilinx/xilinx_vdma.c:1808:23: error: 'segment' may be used uninitialized in this function [-Werror=maybe-uninitialized] segment->hw.control |= XILINX_DMA_BD_SOP; This can only happen if the period len is zero (which would cause other problems earlier), or if the buffer is shorter than a period. Neither of them should ever happen, but by adding an explicit check for these two cases, we can abort in a more controlled way, and the compiler is able to see that we never use uninitialized data. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-13dmaengine: vdma: Fix compilation warning in cyclic dma modeKedareswara rao Appana
This patch fixes the below compilation warining. drivers/dma/xilinx/xilinx_vdma.c: In function 'xilinx_dma_prep_dma_cyclic': drivers/dma/xilinx/xilinx_vdma.c:1808:23: warning: 'segment' may be used uninitialized in this function [-Wmaybe-uninitialized] segment->hw.control |= XILINX_DMA_BD_SOP; The start of packet (SOP) should be set to the first segment in the desc chain not for the last segment of the desc chain. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-07dmaengine: vdma: Use dma_pool_zallocKedareswara rao Appana
dma_pool_zalloc combines dma_pool_alloc and memset 0 this patch updates the driver to use dma_pool_zalloc. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-06-07dmaengine: vdma: Add support for cyclic dma modeKedareswara rao Appana
This patch adds support for AXI DMA cyclic dma mode. In cyclic mode, DMA fetches and processes the same BDs without interruption. The DMA continues to fetch and process until it is stopped or reset. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-19Merge tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds
Pull dmaengine updates from Vinod Koul: "This time round the update brings in following changes: - new tegra driver for ADMA device - support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI Central Direct Memory Access Engine and few updates to this driver - new cyclic capability to sun6i and few updates - slave-sg support in bcm2835 - updates to many drivers like designware, hsu, mv_xor, pxa, edma, qcom_hidma & bam" * tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits) dmaengine: ioatdma: disable relaxed ordering for ioatdma dmaengine: of_dma: approximate an average distribution dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event dmaengine: qcom_hidma: add support for object hierarchy dmaengine: qcom_hidma: add debugfs hooks dmaengine: qcom_hidma: implement lower level hardware interface dmaengine: vdma: Add clock support Documentation: DT: vdma: Add clock support for dmas dmaengine: vdma: Add config structure to differentiate dmas MAINTAINERS: Update Tegra DMA maintainers dmaengine: tegra-adma: Add support for Tegra210 ADMA Documentation: DT: Add binding documentation for NVIDIA ADMA dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine Documentation: DT: vdma: update binding doc for AXI CDMA dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine Documentation: DT: vdma: update binding doc for AXI DMA dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC ...
2016-05-13dmaengine: vdma: Add clock supportKedareswara rao Appana
Added basic clock support for axi dma's. The clocks are requested at probe and released at remove. Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-13dmaengine: vdma: Add config structure to differentiate dmasKedareswara rao Appana
This patch adds config structure in the driver to differentiate AXI DMA's and to add more features(clock support etc..) to these DMA's. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access EngineKedareswara rao Appana
This patch adds support for the AXI Central Direct Memory Access (AXI CDMA) core to the existing vdma driver, AXI CDMA is a soft Xilinx IP core that provides high-bandwidth Direct Memory Access(DMA) between a memory-mapped source address and a memory-mapped destination address. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access EngineKedareswara rao Appana
This patch adds support for the AXI Direct Memory Access (AXI DMA) core in the existing vdma driver, AXI DMA Core is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream type target peripherals. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-12dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dmaKedareswara rao Appana
This patch renames the xilinx_vdma_ prefix to xilinx_dma for the API's and masks that will be shared b/w three DMA IP cores. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-05-03dmaengine: vdma: Use dma_pool_zallocJulia Lawall
Dma_pool_zalloc combines dma_pool_alloc and memset 0. The semantic patch that makes this transformation is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression d,e; statement S; @@ d = - dma_pool_alloc + dma_pool_zalloc (...); if (!d) S - memset(d, 0, sizeof(*d)); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06dmaengine: vdma: Fix checkpatch.pl warningsKedareswara rao Appana
This patch fixes the below checkpatch.pl warnings. WARNING: void function return statements are not generally useful + return; +} WARNING: void function return statements are not generally useful + return; +} WARNING: Missing a blank line after declarations + u32 errors = status & XILINX_VDMA_DMASR_ALL_ERR_MASK; + vdma_ctrl_write(chan, XILINX_VDMA_REG_DMASR, Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06dmaengine: vdma: Fix race condition in Non-SG modeKedareswara rao Appana
When VDMA is configured in Non-sg mode Users can queue descriptors greater than h/w configured frames. Current driver allows the user to queue descriptors upto h/w configured. Which is wrong for non-sg mode configuration. This patch fixes this issue. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-06dmaengine: vdma: Add 64 bit addressing support to the driverKedareswara rao Appana
This VDMA is a soft ip, which can be programmed to support 32 bit addressing or greater than 32 bit addressing. When the VDMA ip is configured for 32 bit address space the buffer address is specified by a single register (0x5C for MM2S and 0xAC for S2MM channel). When the VDMA core is configured for an address space greater than 32 then each buffer address is specified by a combination of two registers. The first register specifies the LSB 32 bits of address, while the next register specifies the MSB 32 bits of address. For example, 5Ch will specify the LSB 32 bits while 60h will specify the MSB 32 bits of the first start address. So we need to program two registers at a time. This patch adds the 64 bit addressing support to the vdma driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-04-05dmaengine: vdma: don't crash when bad channel is requestedFranck Jullien
When client request a non existing channel from of_dma_xilinx_xlate we get a NULL pointer dereferencing. This patch fix this problem. Signed-off-by: Franck Jullien <franck.jullien@odyssee-systemes.fr> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-04dmaengine: xilinx_vdma: Remove unnecessary variable initializationsKedareswara rao Appana
This patch removes the unnecessary variable initializations in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2016-03-03dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop'sKedareswara rao Appana
It is sometimes necessary to poll a memory-mapped register until its value satisfies some condition use convenience macros that do this instead of do while loop's. This patch updates the same in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>