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path: root/drivers/crypto/hisilicon
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2020-06-15crypto: hisilicon - Cap block size at 2^31Herbert Xu
The function hisi_acc_create_sg_pool may allocate a block of memory of size PAGE_SIZE * 2^(MAX_ORDER - 1). This value may exceed 2^31 on ia64, which would overflow the u32. This patch caps it at 2^31. Reported-by: kernel test robot <lkp@intel.com> Fixes: d8ac7b85236b ("crypto: hisilicon - fix large sgl memory...") Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-28crypto: hisilicon - fix driver compatibility issue with different versions ↵Weili Qian
of devices In order to be compatible with devices of different versions, V1 in the accelerator driver is now isolated, and other versions are the previous V2 processing flow. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-23crypto: hisilicon/qm - change debugfs file name from qm_regs to regsShukun Tan
The debugfs qm_regs file is already in the qm directory, so no qm_ prefix is required. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-23crypto: hisilicon/qm - add DebugFS for xQC and xQE dumpShukun Tan
Add dump information of SQC/CQC/EQC/AEQC/SQE/CQE/EQE/AEQE. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-23crypto: hisilicon/zip - add debugfs for Hisilicon ZIPLongfang Liu
Hisilicon ZIP engine driver uses debugfs to provides IO operation debug information Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-23crypto: hisilicon/hpre - add debugfs for Hisilicon HPREHui Tang
Add debugfs to provides IO operation debug information and add BD processing timeout count function Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-23crypto: hisilicon/sec2 - add debugfs for Hisilicon SECKai Ye
Hisilicon SEC engine driver uses debugfs to provides IO operation debug information Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-23crypto: hisilicon/qm - add debugfs to the QM state machineLongfang Liu
The QM driver uses debugfs to provides the current state of the QM state machine Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-23crypto: hisilicon/qm - add debugfs for QMLongfang Liu
Add DebugFS method to get the information of IRQ/Requests/QP .etc of QM for HPRE/ZIP/SEC drivers. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/zip - Use temporary sqe when doing workZhou Wang
Currently zip sqe is stored in hisi_zip_qp_ctx, which will bring corruption with multiple parallel users of the crypto tfm. This patch removes the zip_sqe in hisi_zip_qp_ctx and uses a temporary sqe instead. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon - add device error report through abnormal irqShukun Tan
By configuring the device error in firmware to report through abnormal interruption, process all NFE errors in irq handler. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon - remove codes of directly report device errors through MSIShukun Tan
The hardware device can be configured to report directly through MSI, but this method will not go through RAS, configure all hardware errors that should be processed by driver to NFE. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon - QM memory management optimizationWeili Qian
Put all the code for the memory allocation into the QM initialization process. Before, The qp memory was allocated when the qp was created, and released when the qp was released, It is now changed to allocate all the qp memory once. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon - unify initial value assignment into QMWeili Qian
Some initial value assignment of struct hisi_qm could put into QM. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon - remove use_dma_api related codesShukun Tan
The codes related use_dma_api is useless which should be removed. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon - add FLR supportShukun Tan
Add callback reset_prepare and reset_done in QM, The callback reset_prepare will uninit device error configuration and stop the QM, the callback reset_done will init the device error configuration and restart the QM. Uninit the error configuration will disable device block master OOO when Multi-bit ECC error occurs to avoid the request of FLR will not return. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/qm - add state machine for QMZhou Wang
Add specific states for qm and qp, every state change under critical region to prevent from race condition. Meanwhile, qp state change will also depend on qm state. Due to the introduction of these states, it is necessary to pay attention to the calls of public logic, such as concurrent scenarios resetting and releasing queue will call hisi_qm_stop, which needs to add additional status to distinguish and process. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon - refactor module parameter pf_q_num related codeShukun Tan
put q_num_set similar code into qm to reduce the redundancy. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/zip - modify the ZIP probe processLongfang Liu
Misc fixes on coding style: 1.Merge QM initialization code into a function 2.Merge QM's PF and VF initialization into a function Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/hpre - modify the HPRE probe processLongfang Liu
Misc fixes on coding style: 1.Merge pre-initialization and initialization of QM 2.Package the initialization of QM's PF and VF into a function Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/sec2 - modify the SEC probe processLongfang Liu
Adjust the position of SMMU status check and SEC queue initialization in SEC probe Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/sec2 - constify sec_dfx_regsRikard Falkeborn
sec_dfx_regs is never changed and can therefore be made const. This allows the compiler to put it in the text section instead of the data section. Before: text data bss dec hex filename 17982 7312 480 25774 64ae drivers/crypto/hisilicon/sec2/sec_main.o After: text data bss dec hex filename 18366 6928 480 25774 64ae drivers/crypto/hisilicon/sec2/sec_main.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/zip - constify struct debugfs_reg32Rikard Falkeborn
hzip_dfx_regs is never changed and can be made const. This allows the compiler to put it in the text section instead of the data section. Before: text data bss dec hex filename 15236 6160 480 21876 5574 drivers/crypto/hisilicon/zip/zip_main.o After: text data bss dec hex filename 15620 5776 480 21876 5574 drivers/crypto/hisilicon/zip/zip_main.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-15crypto: hisilicon/hpre - constify struct debugfs_reg32Rikard Falkeborn
hpre_cluster_dfx_regs and hpre_com_dfx_regs are never changed and can therefore be made const. This allows the compiler to put it in the text section instead of the data section. Before: text data bss dec hex filename 16455 6288 480 23223 5ab7 drivers/crypto/hisilicon/hpre/hpre_main.o After: text data bss dec hex filename 16839 5904 480 23223 5ab7 drivers/crypto/hisilicon/hpre/hpre_main.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-05-08crypto: hisilicon/sec2 - use crypto_shash_tfm_digest()Eric Biggers
Instead of manually allocating a 'struct shash_desc' on the stack and calling crypto_shash_digest(), switch to using the new helper function crypto_shash_tfm_digest() which does this for us. Cc: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-30crypto: hisilicon/qm - Make qm_controller_reset() staticZou Wei
Fix the following sparse warning: drivers/crypto/hisilicon/qm.c:3079:5: warning: symbol 'qm_controller_reset' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-22crypto: hisilicon/qm - add more ACPI dependenciesStephen Rothwell
due to the selects of CRYPTO_DEV_HISI_QM which now depends on ACPI Fixes: 6c6dd5802c2d ("crypto: hisilicon/qm - add controller reset...") Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-20crypto: hisilicon/qm - fix build failure with ACPI offShukun Tan
Add Kconfig dependency to fix kbuild warnings. Fixes: 6c6dd5802c2d ("crypto: hisilicon/qm - add controller reset interface") Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon/qm - stop qp by judging sq and cq tailYang Shen
It is not working well to determine whether the queue is empty based on whether the used count is 0. It is more stable to get if the queue is stopping by checking if the tail pointer of the send queue and the completion queue are equal. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon/sec2 - add controller reset support for SEC2Yang Shen
Add support for controller reset in SEC driver. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon/hpre - add controller reset support for HPREHui Tang
Add support for the controller reset in HPRE driver. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon/zip - add controller reset support for zipShukun Tan
Register controller reset handle with PCIe AER. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon/qm - add controller reset interfaceShukun Tan
Add the main implementation of the controller reset interface, which is roughly divided into three parts, stop, reset, and reinitialization. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon - add vfs_num module parameter for hpre/secHao Fang
The vfs_num module parameter has been used in zip driver, this patch adds this for HPRE and SEC driver. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon - unify SR-IOV related codes into QMShukun Tan
Clean the duplicate SR-IOV related codes, put all into qm.c. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-16crypto: hisilicon - put vfs_num into struct hisi_qmShukun Tan
We plan to move vfs_num related code into qm.c, put the param vfs_num into struct hisi_qm first. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-04-03crypto: hisilicon - Fix build errorYueHaibing
When UACCE is m, CRYPTO_DEV_HISI_QM cannot be built-in. But CRYPTO_DEV_HISI_QM is selected by CRYPTO_DEV_HISI_SEC2 and CRYPTO_DEV_HISI_HPRE unconditionally, which may leads this: drivers/crypto/hisilicon/qm.o: In function 'qm_alloc_uacce': drivers/crypto/hisilicon/qm.c:1579: undefined reference to 'uacce_alloc' Add Kconfig dependency to enforce usable configurations. Fixes: 47c16b449921 ("crypto: hisilicon - qm depends on UACCE") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-20crypto: hisilicon/sec2 - Add new create qp processKai Ye
Combine found device and created qp into one operation instead of found device and create qp both are independent operations. when execute multiple tasks, the different threads may find same device at the same time, but the number of queues is insufficient on the device. causing one of threads fail to create a qp. Now fix this, First find device then create qp, if result failure. the current thread will find next device. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-20crypto: hisilicon/hpre - Optimize finding hpre device processHui Tang
Optimize finding hpre device process according to priority of numa distance. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-20crypto: hisilicon/zip - Use hisi_qm_alloc_qps_node() when init ctxShukun Tan
Encapsulate hisi_qm_alloc_qps_node() to new interface to replace find_zip_device(), which will fix the bug of creating QP failure especially in multi-thread scenario. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-20crypto: hisilicon/qm - Put device finding logic into QMWeili Qian
Use struct hisi_qm to maintain device list. Meanwhile, add two external interface into qm, merge find proper device and create qp into QP alloc logic, merge release qps into QP free logic. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-12crypto: hisilicon/sec2 - Add pbuffer mode for SEC driverLongfang Liu
In the scenario of SMMU translation, the SEC performance of short messages (<512Bytes) cannot meet our expectations. To avoid this, we reserve the plat buffer (PBUF) memory for small packets when creating TFM. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-12crypto: hisilicon/sec2 - Update IV and MAC operationLongfang Liu
We have updated the operation method of IV and MAC address to prepare for pbuf patch and fixed coding style. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-12crypto: hisilicon/sec2 - Add iommu status checkLongfang Liu
In order to improve performance of small packets (<512Bytes) in SMMU translation scenario, we need to identify the type of IOMMU in the SEC probe to process small packets by a different method. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-12crypto: hisilicon/sec2 - Add workqueue for SEC driver.Ye Kai
Allocate one workqueue for each QM instead of one for all QMs, we found the throughput of SEC engine can be increased to the hardware limit throughput during testing sec2 performance. so we added this scheme. Signed-off-by: Ye Kai <yekai13@huawei.com> Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-12crypto: hisilicon - Use one workqueue per qm instead of per qpShukun Tan
Since SEC need not so many workqueues as our test, we just use one workqueue created by the device driver of QM if necessary, which will also reduce CPU waste without any throughput decreasing. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-03-06crypto: hisilicon - qm depends on UACCEHongbo Yao
If UACCE=m and CRYPTO_DEV_HISI_QM=y, the following error is seen while building qm.o: drivers/crypto/hisilicon/qm.o: In function `hisi_qm_init': (.text+0x23c6): undefined reference to `uacce_alloc' (.text+0x2474): undefined reference to `uacce_remove' (.text+0x286b): undefined reference to `uacce_remove' drivers/crypto/hisilicon/qm.o: In function `hisi_qm_uninit': (.text+0x2918): undefined reference to `uacce_remove' make[1]: *** [vmlinux] Error 1 make: *** [autoksyms_recursive] Error 2 This patch fixes the config dependency for QM and ZIP. reported-by: Hulk Robot <hulkci@huawei.com> Suggested-by: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Hongbo Yao <yaohongbo@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-02-28crypto: hisilicon - remove redundant assignment of pointer ctxColin Ian King
Pointer ctx is being re-assigned with the same value as it was initialized with. The second assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-02-22crypto: hisilicon - register zip engine to uacceZhangfei Gao
Register qm to uacce framework for user crypto driver Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-02-22crypto: hisilicon - Remove module_param uacce_modeZhangfei Gao
Remove the module_param uacce_mode, which is not used currently. Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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