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path: root/drivers/clocksource/timer-atcpit100.c
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2018-07-26clocksource/drivers: Set clockevent device cpumask to cpu_possible_maskSudeep Holla
Currently, quite a few clockevent devices have cpumask set to cpu_all_mask which should be fine. However, cpu_possible_mask is more accurate and if there are any other clockevent devices in the system which have cpumask set to cpu_possible_mask, then having cpu_all_mask may result in issues (mostly boot hang with forever loops in clockevents_notify_released). So, lets replace all the clockevent device cpu_all_mask to cpu_possible_mask in order to prevent above mentioned possible issue. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2018-02-22clocksource/drivers/atcpit100: VDSO supportRick Chen
VDSO needs real-time cycle count to ensure the time accuracy. Unlike others, nds32 architecture does not define clock source, hence VDSO needs atcpit100 offering real-time cycle count to derive the correct time. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-02-22clocksource/drivers/atcpit100: Add andestech atcpit100 timerRick Chen
ATCPIT100 is often used on the Andes architecture, This timer provide 4 PIT channels. Each PIT channel is a multi-function timer, can be configured as 32,16,8 bit timers or PWM as well. For system timer it will set channel 1 32-bit timer0 as clock source and count downwards until underflow and restart again. It also set channel 0 32-bit timer0 as clock event and count downwards until condition match. It will generate an interrupt for handling periodically. Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Add andestech atcpit100 timer