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Age	Commit message (Expand)	Author
2017-04-04	clk: sunxi-ng: add support for PRCM CCUs	Icenowy Zheng
2017-04-04	clk: tegra: Don't reset PLL-CX if it is already enabled	Jon Hunter
2017-04-04	clk: tegra: Add missing Tegra210 clocks	Peter De Schrijver
2017-04-04	clk: tegra: Propagate clk_out_x rate to parent	Alex Frid
2017-04-03	clk: stm32f4: fix: exclude values 0 and 1 for PLLQ	Gabriel Fernandez
2017-03-30	clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0	Geert Uytterhoeven
2017-03-30	clk: renesas: r8a7795: Add support for R-Car H3 ES2.0	Geert Uytterhoeven
2017-03-30	clk: renesas: cpg-mssr: Add support for fixing up clock tables	Geert Uytterhoeven
2017-03-27	clk: meson: mpll: correct N2 maximum value	Jerome Brunet
2017-03-27	clk: meson8b: add the mplls clocks 0, 1 and 2	Jerome Brunet
2017-03-27	clk: meson: gxbb: mpll: use rw operation	Jerome Brunet
2017-03-27	clk: meson: mpll: add rw operation	Jerome Brunet
2017-03-27	clk: gxbb: put dividers and muxes in tables	Jerome Brunet
2017-03-27	clk: meson8b: put dividers and muxes in tables	Jerome Brunet
2017-03-27	clk: meson: add missing const qualifiers on gate arrays	Jerome Brunet
2017-03-27	clk: meson: fix SET_PARM macro	Jerome Brunet
2017-03-23	Merge tag 'sunxi-clk-fixes-for-4.11' of https://git.kernel.org/pub/scm/linux/...	Stephen Boyd
2017-03-22	clk: rockchip: add pll_wait_lock for pll_enable	Elaine Zhang
2017-03-22	clk: rockchip: rename RK1108 to RV1108	Andy Yan
2017-03-21	clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0	Geert Uytterhoeven
2017-03-21	clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()	Geert Uytterhoeven
2017-03-21	clk: renesas: r8a7796: Reformat core clock table	Geert Uytterhoeven
2017-03-21	clk: renesas: r8a7795: Reformat core clock table	Geert Uytterhoeven
2017-03-21	clk: renesas: r8a7796: Correct name of watchdog clock	Geert Uytterhoeven
2017-03-21	clk: renesas: r8a7795: Correct name of watchdog clock	Geert Uytterhoeven
2017-03-21	clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs	Geert Uytterhoeven
2017-03-20	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding
2017-03-20	clk: tegra: Mark TEGRA210_CLK_DBGAPB as always on	Peter De Schrijver
2017-03-20	clk: tegra: Add SATA seq input control	Peter De Schrijver
2017-03-20	clk: tegra: Add Tegra210 special resets	Peter De Schrijver
2017-03-20	clk: tegra: Rework pll_u	Peter De Schrijver
2017-03-20	clk: tegra: Implement reset control reset	Mikko Perttunen
2017-03-20	clk: tegra: Fix disable unused for clocks sharing enable bit	Peter De Schrijver
2017-03-20	clk: tegra: Handle UTMIPLL IDDQ	Peter De Schrijver
2017-03-20	clk: tegra: Add aclk	Peter De Schrijver
2017-03-20	clk: tegra: Add super clock mux/divider	Peter De Schrijver
2017-03-20	clk: tegra: Define Tegra210 DMIC clocks	Peter De Schrijver
2017-03-20	clk: tegra: Fix constness for peripheral clocks	Peter De Schrijver
2017-03-20	clk: tegra: Define Tegra210 DMIC sync clocks	Peter De Schrijver
2017-03-20	clk: tegra: Add CEC clock	Peter De Schrijver
2017-03-20	clk: tegra: Fix type for m field	Peter De Schrijver
2017-03-20	clk: tegra: Correct tegra210_pll_fixed_mdiv_cfg rate calculation	Peter De Schrijver
2017-03-20	clk: tegra: Don't warn for PLL defaults unnecessarily	Peter De Schrijver
2017-03-20	clk: tegra: Remove non-existing pll_m_out1 clock	Peter De Schrijver
2017-03-20	clk: tegra: Correct afi clock parent	Peter De Schrijver
2017-03-20	clk: tegra: Fix ISP clock modelling	Peter De Schrijver
2017-03-20	clk: tegra: Fix pll_a1 iddq register, add pll_a1	Peter De Schrijver
2017-03-20	clk: sunxi-ng: fix recalc_rate formula of NKMP clocks	Icenowy Zheng
2017-03-20	clk: sunxi-ng: Fix div/mult settings for osc12M on A64	Philipp Tomsich
2017-03-16	clk: meson-gxbb: expose clock CLKID_RNG0	Heiner Kallweit