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2020-12-10clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2Douglas Anderson
50 MHz is an incredibly common clock rate for SD cards to run at. It's "high speed" mode in SD (not very fast these days, but it used to be) or: #define HIGH_SPEED_MAX_DTR 50000000 If we don't support this then older "high speed" cards can only run at 25 MHz or at half their normal speed. There doesn't seem to be any reason to skip this clock rate, so add it. Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201210102234.2.I26dcc0cee374f5571d9929c9985f463773167e68@changeid Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10clk: qcom: gcc-sc7180: Use floor ops for sdcc clksDouglas Anderson
I would repeat the same commit message that was in commit 5e4b7e82d497 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems silly to do so when you could just go read that commit. NOTE: this is actually extra terrible because we're missing the 50 MHz rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2")). That means then when you run an older SD card it'll try to clock it at 100 MHz when it's only specced to run at 50 MHz max. As you can probably guess that doesn't work super well. Signed-off-by: Douglas Anderson <dianders@chromium.org> Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Link: https://lore.kernel.org/r/20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10clk: scpi: mark scpi_clk_match as maybe unusedKrzysztof Kozlowski
The scpi_clk_match (struct of_device_id) is referenced only with CONFIG_OF builds thus mark it as __maybe_unused: drivers/clk/clk-scpi.c:132:34: warning: ‘scpi_clk_match’ defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201103162435.13689-8-krzk@kernel.org Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10clk: pwm: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might be not relevant here). This fixes compile warning (!CONFIG_OF && !CONFIG_MODULES): drivers/clk/clk-pwm.c:139:34: warning: ‘clk_pwm_dt_ids’ defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201103162435.13689-1-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-10clk: renesas: sh73a0: Stop using __raw_*() I/O accessorsGeert Uytterhoeven
There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM driver code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by: Arnd Bergmann <arnd@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201119125053.4065746-1-geert+renesas@glider.be
2020-12-10clk: renesas: r8a774c0: Add RPC clocksLad Prabhakar
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR driver. Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC), parent and the divider is set based on the register value CPG_RPCCKCR[4:3] which has been set prior to booting the kernel. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20201116101002.5986-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10clk: renesas: r8a779a0: Fix R and OSC clocksGeert Uytterhoeven
The R-Car V3U clock driver defines the R and OSC clocks using R-Car Gen3 clock types. However, The R-Car V3U clock driver does not use the R-Car Gen3 clock driver core, hence registering the R and OSC clocks fails: renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock osc: -22 renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock r: -22 Fix this by introducing clock definition macros specific to R-Car V3U. Note that rcar_r8a779a0_cpg_clk_register() already handled the related clock types. Drop the now unneeded include of rcar-gen3-cpg.h. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20201109152614.2465483-1-geert+renesas@glider.be
2020-12-10clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_privKrzysztof Kozlowski
The struct cpg_mssr_priv missed proper formatting: drivers/clk/renesas/renesas-cpg-mssr.c:142: warning: cannot understand function prototype: 'struct cpg_mssr_priv ' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201103162435.13689-7-krzk@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()Yejune Deng
devm_reset_control_array_get_shared() looks more readable Signed-off-by: Yejune Deng <yejune.deng@gmail.com> Link: https://lore.kernel.org/r/1604375093-6451-1-git-send-email-yejune.deng@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10clk: renesas: r8a774b1: Add RPC clocksBiju Das
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20201016121709.8447-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10clk: renesas: r8a774a1: Add RPC clocksBiju Das
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20201016121709.8447-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10clk: renesas: r8a779a0: Add VIN clocksJacopo Mondi
Add definitions of the VIN instance clocks for R-Car V3U. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20201016111158.17521-5-jacopo+renesas@jmondi.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10clk: renesas: r8a779a0: Add CSI4[0-3] clocksJacopo Mondi
Add definitions of the CSI-2 receiver clocks for R-Car V3U. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20201016111158.17521-2-jacopo+renesas@jmondi.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-12-10clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() staticGeert Uytterhoeven
When compiling with clang: drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:21: warning: no previous prototype for function 'rcar_r8a779a0_cpg_clk_register' [-Wmissing-prototypes] struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, ^ drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:1: note: declare 'static' if the function is not intended to be used outside of this translation unit struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, ^ static Similarly, with sparse: drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:12: warning: symbol 'rcar_r8a779a0_cpg_clk_register' was not declared. Should it be static? There are no users of rcar_r8a779a0_cpg_clk_register() outside this file, so it should be static. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200924111808.15358-1-geert+renesas@glider.be
2020-12-09Merge tag 'samsung-drivers-5.11-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung SoC drivers changes for v5.11, part two 1. Mark PM functions of newly added clkout module as unused to silence !CONFIG_PM warnings. 2. Initialize ChipID driver later - in arch initcall. * tag 'samsung-drivers-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: mark PM functions as __maybe_unused soc: samsung: exynos-chipid: initialize later - with arch_initcall soc: samsung: exynos-chipid: order list of SoCs by name Link: https://lore.kernel.org/r/20201207074528.4475-1-krzk@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-09Merge tag 'omap-for-v5.11/genpd-drivers-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/drivers Driver changes for omaps for genpd for v5.11 merge window This series of changes allows booting am335x with genpd and device tree data without the legacy platform data. Also at least am437x can be booted with gendp with power domain and dts data. The SoC specific dts changes will be a separate pull request. We need the following driver changes merged before the dts changes can be done: - platform code needs a few improvments to probe l4_wkup first for clocks, and to bail out when there is no platform data - ti-sysc driver needs a non-urgent fix for asserting rstctrl reset only after disabling the clocks, to probe modules with no known control registers, and added quirk handling for gpmc devices - omap-prm driver needs a non-urgent fix for reset status bit, support added for pm_clk, and then we add the rest of am335x power domain data - clock driver for am335x needs to keep l3_main clock enabled with genpd for suspend and resume to work - wkup_m3 remoteproc driver needs support added for reset control if available instead of the legacy pdata callbacks - pm33xx driver needs PM runtime support added for genpd The am335x specific driver changes for the clock, wkup_m3, pm33xx and remoteproc drivers are quite trivial and have not caused merge conflicts in Linux next. I did not get acks for these changes except from Santosh but had already pushed out the branch already at that point. So I've added the related driver maintainers to Cc. * tag 'omap-for-v5.11/genpd-drivers-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: remoteproc/wkup_m3: Use reset control driver if available soc: ti: pm33xx: Enable basic PM runtime support for genpd soc: ti: omap-prm: am3: add genpd support for remaining PRM instances soc: ti: omap-prm: Add pm_clk for genpd clk: ti: am33xx: Keep am3 l3 main clock always on for genpd bus: ti-sysc: Implement GPMC debug quirk to drop platform data bus: ti-sysc: Support modules without control registers ARM: OMAP2+: Probe PRCM first to probe l4_wkup with simple-pm-bus ARM: OMAP2+: Check for inited flag bus: ti-sysc: Assert reset only after disabling clocks soc: ti: omap-prm: Do not check rstst bit on deassert if already deasserted bus: ti-sysc: Fix bogus resetdone warning on enable for cpsw bus: ti-sysc: Fix reset status check for modules with quirks ARM: OMAP2+: Fix missing select PM_GENERIC_DOMAINS_OF ARM: OMAP2+: Fix location for select PM_GENERIC_DOMAINS Link: https://lore.kernel.org/r/pull-1606806458-694517@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-07clk: qcom: Add GDSC support for SDX55 GCCManivannan Sadhasivam
Add GDSC support to control the power supply of power domains in SDX55 GCC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201126072844.35370-7-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: qcom: Add support for SDX55 RPMh clocksManivannan Sadhasivam
Add support for following clocks maintained by RPMh in SDX55 SoCs. * BI TCXO * RF_CLK1 * RF_CLK1_AO * RF_CLK2 * RF_CLK2_AO * QPIC (Qualcomm Technologies, Inc. Parallel Interface Controller) Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20201126072844.35370-5-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: qcom: Add SDX55 GCC supportNaveen Yadav
Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. Signed-off-by: Naveen Yadav <naveenky@codeaurora.org> [mani: converted to parent_data, commented critical clocks, cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20201126072844.35370-3-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: fsl-flexspi: new driverMichael Walle
Add support for the FlexSPI clock on Freescale Layerscape SoCs. The clock is a simple divider based one and is located inside the device configuration space (DCFG). This will allow switching the SCK frequencies for the FlexSPI interface on the LS1028A and the LX2160A. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20201108185113.31377-8-michael@walle.cc [sboyd@kernel.org: Drop modalias, add module table] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: divider: add devm_clk_hw_register_divider_table()Michael Walle
This will simplify drivers which would only unregister the clk in their remove() op. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20201108185113.31377-6-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: qoriq: provide constants for the typeMichael Walle
To avoid future mistakes in the device tree for the clockgen module, add constants for the clockgen subtype as well as a macro for the PLL divider. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201108185113.31377-4-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: fsl-sai: use devm_clk_hw_register_composite_pdata()Michael Walle
Simplify the driver by using that helper and drop the remove() function. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20201105192746.19564-4-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: composite: add devm_clk_hw_register_composite_pdata()Michael Walle
This will simplify drivers which would only unregister the clk in their remove() op. Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20201105192746.19564-3-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: fsl-sai: fix memory leakMichael Walle
If the device is removed we don't unregister the composite clock. Fix that. Fixes: 9cd10205227c ("clk: fsl-sai: new driver") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20201105192746.19564-2-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: qoriq: Add platform dependenciesGeert Uytterhoeven
The Freescale QorIQ clock controller is only present on Freescale E500MC and Layerscape SoCs. Add platform dependencies to the CLK_QORIQ config symbol, to avoid asking the user about it when configuring a kernel without E500MC or Layerscape support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20201110154750.3285411-1-geert+renesas@glider.be Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: renesas: r9a06g032: Drop __packed for portabilityGeert Uytterhoeven
The R9A06G032 clock driver uses an array of packed structures to reduce kernel size. However, this array contains pointers, which are no longer aligned naturally, and cannot be relocated on PPC64. Hence when compile-testing this driver on PPC64 with CONFIG_RELOCATABLE=y (e.g. PowerPC allyesconfig), the following warnings are produced: WARNING: 136 bad relocations c000000000616be3 R_PPC64_UADDR64 .rodata+0x00000000000cf338 c000000000616bfe R_PPC64_UADDR64 .rodata+0x00000000000cf370 ... Fix this by dropping the __packed attribute from the r9a06g032_clkdesc definition, trading a small size increase for portability. This increases the 156-entry clock table by 1 byte per entry, but due to the compiler generating more efficient code for unpacked accesses, the net size increase is only 76 bytes (gcc 9.3.0 on arm32). Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20201130085743.1656317-1-geert+renesas@glider.be Tested-by: Stephen Rothwell <sfr@canb.auug.org.au> # PowerPC allyesconfig build Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-07clk: imx: scu: fix MXC_CLK_SCU module build breakDong Aisheng
This issue can be reproduced by having a kernel config with CONFIG_IMX_MBOX=m and CONFIG_MXC_CLK_SCU=m. It's caused by the Makefile wanting to build clk-scu.o and clk-imx8qxp.o as different targets but that doesn't work (e.g. MXC_CLK_SCU = y while CLK_IMX8QXP = n) "obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o" Having MXC_CLK_SCU=y/m while CLK_IMX8QXP=n will cause a linker problem like below: LD [M] drivers/clk/imx/clk-imx-scu.o arm-poky-linux-gnueabi-ld: no input files Make MXC_CLK_SCU be un-selectable by users so it can only be selected by the CLK_IMX8QXP option, ensuring the two symbols are built together. Drop COMPILE_TEST too because this option isn't selectable anymore. We can remove it from MXC_CLK_SCU because CLK_IMX8QXP selects MXC_CLK_SCU which already has COMPILE_TEST. Fixes: e0d0d4d86c766 ("clk: imx8qxp: Support building i.MX8QXP clock driver as module") Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20201130084624.21113-1-aisheng.dong@nxp.com [sboyd@kernel.org: Rework commit text] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-05clk: samsung: mark PM functions as __maybe_unusedArnd Bergmann
The use of SIMPLE_DEV_PM_OPS() means that the suspend/resume functions are now unused when CONFIG_PM is disabled: drivers/clk/samsung/clk-exynos-clkout.c:219:12: error: 'exynos_clkout_resume' defined but not used [-Werror=unused-function] 219 | static int exynos_clkout_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ drivers/clk/samsung/clk-exynos-clkout.c:210:12: error: 'exynos_clkout_suspend' defined but not used [-Werror=unused-function] 210 | static int exynos_clkout_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ Mark them as __maybe_unused to shut up the otherwise harmless warning. Fixes: 9484f2cb8332 ("clk: samsung: exynos-clkout: convert to module driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Link: https://lore.kernel.org/r/20201204091616.4128366-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-11-30clk: imx: scu: remove the calling of device_is_boundDong Aisheng
The device_is_bound() is invisible to drivers when built as modules. It's also not aimed to be used by drivers according to Greg K.H. Let's remove it from clk-scu driver and find another way to do proper driver loading sequence. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Boyd <sboyd@kernel.org> Fixes: 77d8f3068c63 ("clk: imx: scu: add two cells binding support") Reported-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-11-29clk: rockchip: fix i2s gate bits on rk3066 and rk3188Johan Jonker
The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON: hclk_i2s_8ch_gate_en bit 4 (dtsi: i2s0) hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1) hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2) The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON: hclk_i2s_2ch_gate_en bit 2 (dtsi: i2s0) The bits got somehow mixed up in the clk-rk3188.c file. The labels in the dtsi files are not suppose to change. The sclk and hclk names should match for "trace_event=clk_disable,clk_enable", so remove GATE HCLK_I2S0 from the common clock tree and fix the bits in the rk3066 and rk3188 clock tree. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201118135822.9582-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-29clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocksJohan Jonker
Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks, so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX also update. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-29clk: rockchip: Remove redundant null check before clk_prepare_enableXu Wang
Because clk_prepare_enable() already checked NULL clock parameter, so the additional check is unnecessary, just remove it. Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201127090551.50254-1-vulab@iscas.ac.cn Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-11-27clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"Colin Ian King
There is a spelling mistake in the Kconfig help text. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20201126232400.15011-1-colin.king@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-26Merge tag 'memory-controller-drv-tegra-5.11-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v5.11 - Tegra SoC There is a bigger work from Dmitry Osipenko around Tegra SoC memory controller drivers, mostly towards adding interconnect support and integration with devfreq. This work touches all Tegra memory controller drivers and also few other SoC-related parts. It's not yet finished but the intermediate stage seems ready to merge. Beside that Tegra 210 memory controller got few fixes and received new swgroups (work of Nicolin Chen). * tag 'memory-controller-drv-tegra-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (38 commits) memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probe memory: tegra: Complete tegra210_swgroups memory: tegra30-emc: Continue probing if timings are missing in device-tree memory: tegra30-emc: Make driver modular memory: tegra30: Add FIFO sizes to memory clients memory: tegra20-emc: Add devfreq support memory: tegra20-emc: Remove IRQ number from error message memory: tegra20-emc: Factor out clk initialization memory: tegra20-emc: Use dev_pm_opp_set_clkname() memory: tegra: Correct stub of devm_tegra_memory_controller_get() memory: tegra20: Support interconnect framework memory: tegra20-emc: Continue probing if timings are missing in device-tree memory: tegra20-emc: Make driver modular memory: tegra-mc: Add interconnect framework memory: tegra: Add missing latency allowness entry for Page Table Cache memory: tegra: Remove superfluous error messages around platform_get_irq() memory: tegra: Use devm_platform_ioremap_resource() memory: tegra: Add and use devm_tegra_memory_controller_get() dt-bindings: host1x: Document new interconnect properties dt-bindings: tegra30-actmon: Document OPP and interconnect properties ... Link: https://lore.kernel.org/r/20201126191241.23302-1-krzk@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-11-26clk: tegra: bpmp: Clamp clock rates on requestsSivaram Nair
BPMP firmware ABI expects the rate inputs in int64_t. However, tegra_bpmp_clk_round_rate() and tegra_bpmp_clk_set_rate() functions directly assign 'unsigned long' inputs to a int64_t value causing unexpected rounding errors. Fix this by clipping the input rate to S64_MAX. Signed-off-by: Sivaram Nair <sivaramn@nvidia.com> [mperttunen: slight cleanup] Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Sivaram Nair <sivaramn@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-26clk: meson: g12a: add MIPI DSI Host Pixel ClockNeil Armstrong
This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201126141600.2084586-3-narmstrong@baylibre.com
2020-11-24clk: qcom: rpmh: Add CE clock on sdm845.Thara Gopinath
Qualcomm CE clock resource that is managed by BCM is required by crypto driver to access the core clock. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org> Link: https://lore.kernel.org/r/20201119155233.3974286-3-thara.gopinath@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-23clk: samsung: Prevent potential endless loop in the PLL opsSylwester Nawrocki
The PLL status polling loops in the set_rate callbacks of some PLLs have no timeout detection and may become endless loops when something goes wrong with the PLL. For some PLLs there is already the ktime API based timeout detection, but it will not work in all conditions when .set_rate gets called. In particular, before the clocksource is initialized or when the timekeeping is suspended. This patch adds a common helper with the PLL status bit polling and timeout detection. For conditions where the timekeeping API should not be used a simple readl_relaxed/cpu_relax() busy loop is added with the iterations limit derived from measurements of readl_relaxed() execution time for various PLL types and Exynos SoCs variants. Actual PLL lock time depends on the P divider value, the VCO frequency and a constant PLL type specific LOCK_FACTOR and can be calculated as lock_time = Pdiv * LOCK_FACTOR / VCO_freq For the ktime API use cases a common timeout value of 20 ms is applied for all the PLLs with an assumption that maximum possible value of Pdiv is 64, maximum possible LOCK_FACTOR value is 3000 and minimum VCO frequency is 24 MHz. Link: https://lore.kernel.org/r/20201120155731.26898-1-s.nawrocki@samsung.com Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-11-23clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210Krzysztof Kozlowski
So far all Exynos, S3C64xx and S5Pv210 clock units were selected by respective SOC/ARCH Kconfig option. On a kernel built for selected SoCs, this allowed to build only limited set of matching clock drivers. However compile testing was not possible in such case as Makefile object depends on SOC/ARCH option. Add separate Kconfig options for each of them to be able to compile test. Link: https://lore.kernel.org/r/20201119164509.754851-1-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-11-23clk: meson: enable building as modulesKevin Hilman
Make it possible to build all clk drivers as modules, but default remains built-in. No functional changes. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201118191405.36798-1-khilman@baylibre.com
2020-11-23clk: meson: Kconfig: fix dependency for G12AKevin Hilman
When building only G12A, ensure that VID_PLL_DIV clock driver is selected, otherwise results in this build error: ERROR: modpost: "meson_vid_pll_div_ro_ops" [drivers/clk/meson/g12a.ko] undefined! Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201118190930.34352-1-khilman@baylibre.com
2020-11-23clk: meson: axg: add MIPI DSI Host clockNeil Armstrong
This adds the MIPI DSI Host clock, used to measure the signal timings (ENC VSYNC or DW-MIPI-DSI eDPI timings). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200915124553.8056-5-narmstrong@baylibre.com
2020-11-23clk: meson: axg: add Video ClocksNeil Armstrong
Add the clocks entries used in the video clock path, the clock path is doubled to permit having different synchronized clocks for different parts of the video pipeline. The AXG only has a single ENCL CTS clock and even if VCLK exist along VCLK2, only VCLK2 is used since it clocks the MIPI DSI IP directly. All dividers are flagged with CLK_GET_RATE_NOCACHE, and all gates are flagged with CLK_IGNORE_UNUSED since they are currently directly handled by the Meson DRM Driver. Once the DRM Driver is fully migrated to using the Common Clock Framework to handle the video clock tree, the CLK_GET_RATE_NOCACHE and CLK_IGNORE_UNUSED will be dropped. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200915124553.8056-4-narmstrong@baylibre.com
2020-11-20clk: tegra: Do not return 0 on failureNicolin Chen
Return values from read_dt_param() will be either TRUE (1) or FALSE (0), while dfll_fetch_pwm_params() returns 0 on success or an ERR code on failure. So this patch fixes the bug of returning 0 on failure. Fixes: 36541f0499fe ("clk: tegra: dfll: support PWM regulator control") Cc: <stable@vger.kernel.org> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-11-19clk: ti: dra7: Drop idlest polling from IVA clkctrl clocksTony Lindgren
Similar to what we've done for IPU and DSP let's ignore the status bit for the IVA clkctrl register. The clkctrl status won't change unless the related rstctrl is deasserted, and the rstctrl status won't change unless the clkctrl is enabled. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Suman Anna <s-anna@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-19clk: ti: omap4: Drop idlest polling from IVA clkctrl clocksTony Lindgren
Similar to what we've done for IPU and DSP let's ignore the status bit for the IVA clkctrl register. The clkctrl status won't change unless the related rstctrl is deasserted, and the rstctrl status won't change unless the clkctrl is enabled. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Suman Anna <s-anna@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-16clk: ti: am437x: Keep am4 l3 main clock always on for genpdTony Lindgren
In order for suspend and resume to work with genpd on am4, we must keep l3 main clock always on. Otherwise prm_omap driver will shut down the l3 main clock on suspend when simple-pm-bus and GENPD_FLAG_PM_CLK are used. Note that we already keep the l3 main clock always on with the legacy platform code. Later on we may want to start managing the l3 main clock with a dedicated interconnect driver instead of using simple-pm-bus and GENPD_FLAG_PM_CLK. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-16clk: ti: am33xx: Keep am3 l3 main clock always on for genpdTony Lindgren
In order for suspend and resume to work with genpd on am3, we must keep l3 main clock always on. Otherwise prm_omap driver will shut down the l3 main clock on suspend when simple-pm-bus and GENPD_FLAG_PM_CLK are used. Note that we already keep the l3 main clock always on with the legacy platform code. Later on we may want to start managing the l3 main clock with a dedicated interconnect driver instead of using simple-pm-bus and GENPD_FLAG_PM_CLK. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-11-14clk: qcom: dispcc-sm8250: handle MMCX power domainDmitry Baryshkov
On SM8250 MMCX power domain is required to access MMDS_GDSC registers. This power domain is expressed as mmcx-supply regulator property. Use this regulator as MDSS_GDSC supply. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20201023131925.334864-6-dmitry.baryshkov@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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