summaryrefslogtreecommitdiff
path: root/drivers/clk
AgeCommit message (Collapse)Author
2019-09-06clk: fix devm_platform_ioremap_resource.cocci warningskbuild test robot
drivers/clk/bcm/clk-bcm63xx-gate.c:174:1-9: WARNING: Use devm_platform_ioremap_resource for hw -> regs Use devm_platform_ioremap_resource helper which wraps platform_get_resource() and devm_ioremap_resource() together. Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci Fixes: 1c099779c1e2 ("clk: add BCM63XX gated clock controller driver") CC: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: kbuild test robot <lkp@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1908081809160.2995@hadrien Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: spear: Make structure i2s_sclk_masks constantNishka Dasgupta
Static structure i2s_sclk_masks, having type aux_clk_masks, is only used when it is passed as the sixth argument to function clk_register_aux(). However, clk_register_aux() is defined with its sixth argument as const. Hence i2s_sclk_masks is not modified by clk_register_aux, which is also the only usage of the former. Therefore make i2s_sclk_masks constant as it is never modified. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Link: https://lkml.kernel.org/r/20190813085714.8079-1-nishkadg.linux@gmail.com Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'YueHaibing
drivers/clk/st/clkgen-pll.c:64:37: warning: st_pll3200c32_407_a0 defined but not used [-Wunused-const-variable=] It is never used, so can be removed. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20190816135523.73520-1-yuehaibing@huawei.com Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'YueHaibing
drivers/clk/st/clkgen-fsyn.c:70:29: warning: st_quadfs_fs660c32_ops defined but not used [-Wunused-const-variable=] It is never used, so can be removed. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20190816135341.52248-1-yuehaibing@huawei.com Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-05clk: Document of_parse_clkspec() some moreStephen Boyd
The return value of of_parse_clkspec() is peculiar. If the function is called with a NULL argument for 'name' it will return -ENOENT, but if it's called with a non-NULL argument for 'name' it will return -EINVAL. This peculiarity is documented by commit 5c56dfe63b6e ("clk: Add comment about __of_clk_get_by_name() error values"). Let's further document this function so that it's clear what the return value is and how to use the arguments to parse clk specifiers. Cc: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190826212042.48642-1-sboyd@kernel.org Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
2019-09-05clk: rockchip: Add clock controller for the rk3308Finley Xiao
Add the clock tree definition for the new RK3308 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-09-04Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann
arm/late mvebu dt64 for 5.4 (part 2) Add support for Turris Mox board (Armada 3720 SoC based) * tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits) arm64: dts: marvell: add DTS for Turris Mox dt-bindings: marvell: document Turris Mox compatible arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl arm64: dts: marvell: Add cpu clock node on Armada 7K/8K arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes arm64: dts: marvell: Add CP110 COMPHY clocks arm64: dts: marvell: armada-37xx: add mailbox node dt-bindings: gpio: Document GPIOs via Moxtet bus drivers: gpio: Add support for GPIOs over Moxtet bus bus: moxtet: Add sysfs and debugfs documentation dt-bindings: bus: Document moxtet bus binding bus: Add support for Moxtet bus reset: Add support for resets provided by SCMI firmware: arm_scmi: Add RESET protocol in SCMI v2.0 dt-bindings: arm: Extend SCMI to support new reset protocol firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels ... Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04Merge tag 'omap-for-v5.4/ti-sysc-sgx-signed' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late SoC glue layer changes for SGX on omap variants for v5.4 For a while we've had omap4 sgx glue layer defined in dts and probed with ti-sysc driver. This allows idling the sgx module for PM, and removes the need for custom platform glue layer code for any further driver changes. We first drop the unused legacy platform data for omap4 sgx. Then for omap5, we need add the missing clkctrl clock data so we can configure sgx. And we configure sgx for omap34xx, omap36xx and am3517. For am335x, we still have a dependency for rstctrl reset driver changes, so that will be added later on. Note that this branch is based on earlier ti-sysc branch for omap36xx glue layer quirk handling. * tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: ARM: dts: Configure interconnect target module for am3517sgx ARM: dts: Configure interconnect target module for omap3 sgx ARM: dts: Configure sgx for omap5 clk: ti: add clkctrl data omap5 sgx ARM: OMAP2+: Drop legacy platform data for omap4 gpu Link: https://lore.kernel.org/r/pull-1567016893-318461@atomide.com-4 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux ↵Greg Kroah-Hartman
into char-misc-next Georgi writes: interconnect patches for 5.4 Here are the interconnect driver updates for the 5.4-rc1 merge window. - New feature is the path tagging support that helps with grouping and aggregating the bandwidth requests into separate buckets based on a tag. - The first user of the path tagging is the Qualcomm sdm845 driver that now implements support for wake/sleep sets. This allows consumer drivers to express their bandwidth needs for the different CPU power states. - New interconnect driver for the qcs404 platforms and a driver that communicates bandwidth requests with remote processor over shared memory. - Cleanups and fixes. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> * tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux: drivers: qcom: Add BCM vote macro to header interconnect: qcom: remove COMPILE_TEST from CONFIG_INTERCONNECT_QCOM_QCS404 interconnect: qcom: Add QCS404 interconnect provider driver interconnect: qcom: Add interconnect RPM over SMD driver dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings interconnect: qcom: Add tagging and wake/sleep support for sdm845 interconnect: Add pre_aggregate() callback interconnect: Add support for path tags
2019-09-03Merge tag 'imx-dt-clkdep-5.4' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX device tree update with new clocks: - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board device tree support. - Add DSP device tree support for i.MX8QXP SoC. * tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: imx8qxp: Add DSP DT node arm64: dts: imx8mn: Add cpu-freq support arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support arm64: dts: imx8mn-ddr4-evk: Add i2c1 support arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support arm64: dts: imx8mn: Add gpio-ranges property arm64: dts: freescale: Add i.MX8MN dtsi support clk: imx8: Add DSP related clocks clk: imx: Add support for i.MX8MN clock driver clk: imx: Add API for clk unregister when driver probe fail clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage dt-bindings: imx: Add clock binding doc for i.MX8MN Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03Merge tag 'amlogic-dt64' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.4 Highlights - new SoCs (G12B family): S922X, A311D - new SoCs (SM1 family): S905X3 - new board: SEI Robotics SEI610 (SM1/S905X3) - new board: Khadas VIM3 (G12B/A311D) - DVFS/CPUfreq support on G12[AB] family * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits) arm64: dts: add support for SM1 based SEI Robotics SEI610 dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings dt-bindings: arm: amlogic: add SM1 bindings arm64: dts: meson-g12b-odroid-n2: enable DVFS arm64: dts: meson-g12b-khadas-vim3: add initial device-tree dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml arm64: dts: amlogic: g12 CPU timers stop in suspend arm64: dts: meson-g12b: support a311d and s922x cpu operating points dt-bindings: arm: amlogic: add support for the Khadas VIM3 dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC arm64: dts: meson: add video decoder entries arm64: dts: meson-gx: add video decoder entry dt-bindings: media: amlogic,vdec: add default compatible arm64: dts: meson: add ethernet fifo sizes arm64: dts: meson-g12b: add cpus OPP tables arm64: dts: meson-g12a: enable DVFS on G12A boards arm64: dts: meson-g12a: add cpus OPP table arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi ... Link: https://lore.kernel.org/r/7hr25fbi4v.fsf@baylibre.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-08-26clk: ti: add clkctrl data omap5 sgxTony Lindgren
Looks like we have sgx clock missing currently so let's add it. Cc: Adam Ford <aford173@gmail.com> Cc: Filip Matijević <filip.matijevic.pz@gmail.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: moaz korena <moaz@korena.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Cc: Philipp Rossak <embed3d@gmail.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Tero Kristo <t-kristo@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: linux-clk@vger.kernel.org Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-08-26clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocksNeil Armstrong
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by having a dedicate tree for each core similar to the CPU0 tree. Like the DSU tree, a supplementaty mux has been added to use the CPU0 frequency instead. But since the cluster only has a single power rail and shares a single PLL, it's not worth adding 3 unsused clock tree, so we add only the mux to select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores. They are set read-only because the early boot stages sets them to select the CPU0 input clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clockNeil Armstrong
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to the CPU clock tree with a supplementaty mux to select the CPU0 clock instead. Leave this as read-only since it's set up by the early boot stages. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26clk: meson: g12a: add support for SM1 GP1 PLLNeil Armstrong
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new DynamIQ Shared Unit of the ARM Cores Complex. This also adds a dedicated set of clock and compatible for SM1. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-24clk: imx: imx8mn: fix audio pll settingPeng Fan
The AUDIO PLL max support 650M, so the original clk settings violate spec. This patch makes the output 786432000 -> 393216000, and 722534400 -> 361267200 to aligned with NXP vendor kernel without any impact on audio functionality and go within 650MHz PLL limit. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-23clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domainGeert Uytterhoeven
The CPG/MSSR Clock Domain driver does not implement the generic_pm_domain.power_{on,off}() callbacks, as the domain itself cannot be powered down. Hence the domain should be marked as always-on by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain code from considering it for power-off, and doing unnessary processing. Note that this only affects RZ/A2 SoCs. On R-Car Gen2 and Gen3 SoCs, the R-Car SYSC driver handles Clock Domain creation, and offloads only device attachment/detachment to the CPG/MSSR driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domainGeert Uytterhoeven
The RZ/N1 Clock Domain driver does not implement the generic_pm_domain.power_{on,off}() callbacks, as the domain itself cannot be powered down. Hence the domain should be marked as always-on by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain code from considering it for power-off, and doing unnessary processing. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domainGeert Uytterhoeven
The CPG/MSTP Clock Domain driver does not implement the generic_pm_domain.power_{on,off}() callbacks, as the domain itself cannot be powered down. Hence the domain should be marked as always-on by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain code from considering it for power-off, and doing unnessary processing. This also gets rid of a boot warning when the Clock Domain contains an IRQ-safe device, e.g. on RZ/A1: sh_mtu2 fcff0000.timer: PM domain cpg_clocks will not be powered off Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-21clk: sunxi-ng: h6: Allow I2S to change parent rateJernej Skrabec
I2S doesn't work if parent rate couldn't be change. Difference between wanted and actual rate is too big. Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-08-20clk: meson: axg-audio: add g12a reset supportJerome Brunet
On the g12a, the register space dedicated to the audio clock also provides some resets. Let the clock controller register a reset provider as well for this SoC family. the axg SoC family does not appear to provide this feature. Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-20drivers: qcom: Add BCM vote macro to headerJordan Crouse
The macro to generate a Bus Controller Manager (BCM) TCS command is used by the interconnect driver but might also be interesting to other drivers that need to construct TCS commands for sub processors so move it out of the sdm845 specific file and into the header. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2019-08-19clk: imx8mn: Add necessary frequency support for ARM PLL tableAnson Huang
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing frequency for ARM PLL table. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: Add missing rate_count assignment for each PLL structureAnson Huang
Add .rate_count assignment which is necessary for searching required PLL rate from the each PLL table. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: fix int pll clk gatePeng Fan
To Frac pll, the gate shift is 13, however to Int PLL the gate shift is 11. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: Add GIC clockLeonard Crestez
This is enabled by default but if it's not explicitly defined and marked as critical then its parent might get turned off. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mn: Fix incorrect parentsLeonard Crestez
* Replace to audio_pll2_clk with audio_pll2_out * Replace sys3_pll2_out with sys_pll3_out * Replace sys1_pll_40m with sys_pll1_40m * qspi parent[2] is sys_pll2_333m not sys_pll1_800m Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mm: Fix incorrect parentsLeonard Crestez
* There is no video_pll2 on imx8mm, replace with dummy * Replace reference to sys_pll3_clk with sys_pll3_out * qspi parent[2] is sys_pll2_333m not sys_pll1_800m Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19clk: imx8mq: Fix sys3 pll referencesLeonard Crestez
The "sys3_pll2_out" CLK was removed in refactoring so all references need to be updated to "sys3_pll_out" Fixes: e9dda4af685f ("clk: imx: Refactor entire sccg pll clk") Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-17clk: Remove extraneous 'for' word in commentsRishi Gupta
An extra 'for' word is grammatically incorrect in the comment 'verifying ops for multi-parent clks'. This commit removes this extra for word. Signed-off-by: Rishi Gupta <gupt21@gmail.com> Link: https://lkml.kernel.org/r/1566023759-7880-1-git-send-email-gupt21@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16clk: composite: Drop unused clk.h includeStephen Boyd
This include isn't used. Drop it. Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815042500.9519-1-sboyd@kernel.org
2019-08-16clk: Fix potential NULL dereference in clk_fetch_parent_index()Martin Blumenstingl
Don't compare the parent clock name with a NULL name in the clk_parent_map. This prevents a kernel crash when passing NULL core->parents[i].name to strcmp(). An example which triggered this is a mux clock with four parents when each of them is referenced in the clock driver using clk_parent_data.fw_name and then calling clk_set_parent(clk, 3rd_parent) on this mux. In this case the first parent is also the HW default so core->parents[i].hw is populated when the clock is registered. Calling clk_set_parent(clk, 3rd_parent) will then go through all parents and skip the first parent because it's hw pointer doesn't match. For the second parent no hw pointer is cached yet and clk_core_get(core, 1) returns a non-matching pointer (which is correct because we are comparing the second with the third parent). Comparing the result of clk_core_get(core, 2) with the requested parent gives a match. However we don't reach this point because right after the clk_core_get(core, 1) mismatch the old code tried to !strcmp(parent->name, NULL) (where the second argument is actually core->parents[i].name, but that was never populated by the clock driver). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lkml.kernel.org/r/20190815223155.21384-1-martin.blumenstingl@googlemail.com Fixes: fc0c209c147f ("clk: Allow parents to be specified without string names") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16clk: Fix falling back to legacy parent string matchingStephen Boyd
Calls to clk_core_get() will return ERR_PTR(-EINVAL) if we've started migrating a clk driver to use the DT based style of specifying parents but we haven't made any DT updates yet. This happens when we pass a non-NULL value as the 'name' argument of of_parse_clkspec(). That function returns -EINVAL in such a situation, instead of -ENOENT like we expected. The return value comes back up to clk_core_fill_parent_index() which proceeds to skip calling clk_core_lookup() because the error pointer isn't equal to -ENOENT, it's -EINVAL. Furthermore, we blindly overwrite the error pointer returned by clk_core_get() with NULL when there isn't a legacy .name member specified in the parent map. This isn't too bad right now because we don't really care to differentiate NULL from an error, but in the future we should only try to do a legacy lookup if we know we might find something. This way DT lookups that fail don't try to lookup based on strings when there isn't any string to match, hiding the error from DT parsing. Fix both these problems so that clk provider drivers can use the new style of parent mapping without having to also update their DT at the same time. This patch is based on an earlier patch from Taniya Das which checked for -EINVAL in addition to -ENOENT return values from clk_core_get(). Fixes: 601b6e93304a ("clk: Allow parents to be specified via clkspec index") Cc: Taniya Das <tdas@codeaurora.org> Cc: Jerome Brunet <jbrunet@baylibre.com> Cc: Chen-Yu Tsai <wens@csie.org> Reported-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190813214147.34394-1-sboyd@kernel.org Tested-by: Taniya Das <tdas@codeaurora.org>
2019-08-16clk: Overwrite clk_hw::init with NULL during clk_register()Stephen Boyd
We don't want clk provider drivers to use the init structure after clk registration time, but we leave a dangling reference to it by means of clk_hw::init. Let's overwrite the member with NULL during clk_register() so that this can't be used anymore after registration time. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Doug Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-10-sboyd@kernel.org Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-08-16clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registeredStephen Boyd
The implementation of clk_hw_get_name() relies on the clk_core associated with the clk_hw pointer existing. If of_clk_hw_register() fails, there isn't a clk_core created yet, so calling clk_hw_get_name() here fails. Extract the name first so we can print it later. Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure") Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16clk: ti: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Tero Kristo <t-kristo@ti.com> Cc: Tony Lindgren <tony@atomide.com> Reported-by: "kernelci.org bot" <bot@kernelci.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815221249.53235-1-sboyd@kernel.org
2019-08-16clk: qcom: Remove error prints from DFS registrationStephen Boyd
These aren't useful and they reference the init structure name. Let's just drop them. Cc: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815160020.183334-5-sboyd@kernel.org Acked-by: Taniya Das <tdas@codeaurora.org>
2019-08-16clk: zx296718: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815160020.183334-3-sboyd@kernel.org
2019-08-16clk: milbeaut: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Sugaya Taichi <sugaya.taichi@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190815160020.183334-2-sboyd@kernel.org
2019-08-16clk: socfpga: deindent code to proper indentationStephen Boyd
This code is indented oddly, causing checkpatch to complain. Indent it properly. Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190814002402.18154-1-sboyd@kernel.org Acked-by: Dinh Nguyen <dinguyen@kernel.org>
2019-08-16clk: sprd: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Chunyan Zhang <zhang.chunyan@linaro.org> Cc: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-8-sboyd@kernel.org Acked-by: Baolin Wang <baolin.wang@linaro.org> Acked-by: Chunyan Zhang <zhang.chunyan@linaro.org>
2019-08-16clk: socfpga: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-7-sboyd@kernel.org Acked-by: Dinh Nguyen <dinguyen@kernel.org>
2019-08-16clk: sirf: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Guo Zeng <Guo.Zeng@csr.com> Cc: Barry Song <Baohua.Song@csr.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-6-sboyd@kernel.org
2019-08-16clk: qcom: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Taniya Das <tdas@codeaurora.org> Cc: Andy Gross <agross@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-5-sboyd@kernel.org Acked-by: Taniya Das <tdas@codeaurora.org>
2019-08-16clk: meson: axg-audio: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-4-sboyd@kernel.org Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-16clk: lochnagar: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Charles Keepax <ckeepax@opensource.cirrus.com> Cc: Richard Fitzgerald <rf@opensource.cirrus.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-3-sboyd@kernel.org Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
2019-08-16clk: actions: Don't reference clk_init_data after registrationStephen Boyd
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20190731193517.237136-2-sboyd@kernel.org [sboyd@kernel.org: Move name to after checking for error or NULL hw] Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-14clk: socfpga: stratix10: fix rate caclulationg for cnt_clksDinh Nguyen
Checking bypass_reg is incorrect for calculating the cnt_clk rates. Instead we should be checking that there is a proper hardware register that holds the clock divider. Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-12clk: ingenic: Use CLK_OF_DECLARE_DRIVER macroPaul Cercueil
By using CLK_OF_DECLARE_DRIVER instead of the CLK_OF_DECLARE macro, we allow the driver to probe also as a platform driver. While this driver does not have code to probe as a platform driver, this is still useful for probing children devices in the case where the device node is compatible with "simple-mfd". Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20190810123620.27238-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-12clk: imx8mq: Unregister clks when of_clk_add_provider failedAnson Huang
When of_clk_add_provider failed, all clks should be unregistered. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 01:39:17 +0000