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path: root/drivers/clk
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2016-01-13clk: remove duplicated COMMON_CLK_NXP record from clk/KconfigVladimir Zapolskiy
Presumably the second COMMON_CLK_NXP config option in drivers/clk/Kconfig appeared after a merge conflict resolution, remove the wrong record of two. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-04Merge tag 'tegra-for-4.5-clk' of ↵Michael Turquette
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next clk: tegra: Changes for v4.5-rc1 This set of changes adds support for the Tegra210 SoC and contains a couple fixes and cleanups.
2016-01-02clk: fix clk-gpio.c with optional clock= DT propertyRussell King
When the clock DT property is not given, of_clk_get_parent_count() returns -ENOENT, which then tries to allocate -2 x 4 bytes of memory, which of course fails, causing the whole driver to fail to create the clock. This causes the SolidRun platforms to fail probing the SDHCI1 interface which is connected to the WiFi. Fix this by detecting errno codes, skipping the allocation, and fixing of_clk_gpio_gate_delayed_register_get() to handle a NULL parent_names array. Fixes: 80eeb1f0f757 ("clk: add gpio controlled clock multiplexer") Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-01-02Merge branch 'clk-rockchip' into clk-nextMichael Turquette
2016-01-02clk: rockchip: fix section mismatches with new child-clocksHeiko Stübner
To model the muxes downstream of fractional dividers we introduced the child property, allowing to describe a direct child clock. The first implementation seems to cause section warnings, as the core clock-tree is marked as initdata while the data pointed to from the child element is not. While there may be some way to also set that missing property in the inline notation I didn't find it, so to actually fix the issue for now move the sub-definitions into separate declarations that can have their own __initdata properties. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31clk: gpio: handle error codes for of_clk_get_parent_count()Brian Norris
We might make bad memory allocations if we get (e.g.) -ENOSYS from of_clk_get_parent_count(). Noticed by Coverity. Fixes: f66541ba02d5 ("clk: gpio: Get parent clk names in of_gpio_clk_setup()") Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Sergej Sawazki <ce3a@gmx.de> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31clk: gpio: fix memory leakSudip Mukherjee
If we fail to allocate parent_name then we are returning but we missed freeing data which has already been allocated. Signed-off-by: Sudip Mukherjee <sudip@vectorindia.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-31Merge branch 'clk-renesas' into clk-nextMichael Turquette
2015-12-31clk: shmobile: r8a7795: Add SATA0 clockUlrich Hecht
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24Merge branch 'clk-bcm2835' into clk-nextMichael Turquette
2015-12-24clk: bcm2835: Add PWM clock supportRemi Pommarel
Register the pwm clock for bcm2835. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: bcm2835: Support for clock parent selectionRemi Pommarel
Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple parent clocks. These clocks divide the rate of a parent which can be selected by setting the proper bits in the clock control register. Previously all these parents where handled by a mux clock. But a mux clock cannot be used because updating clock control register to select parent needs a password to be xor'd with the parent index. This patch get rid of mux clock and make these clocks handle their own parent, allowing them to select the one to use. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: bcm2835: add a round up ability to the clock divisorRemi Pommarel
Make bcm2835_clock_choose_div to optionally round up the chosen MASH divisor so that the resulting average rate will not be higher than the requested one. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24Merge branch 'clk-lpc32xx' into clk-nextMichael Turquette
2015-12-24clk: lpc32xx: add common clock framework driverVladimir Zapolskiy
Add support for all configurable clocks found on NXP LPC32xx SoC. The list contains several heterogenous groups of clocks: * system clocks including multiple dividers and muxes, * x397 PLL, HCLK PLL and USB PLL, * peripheral clocks inherited from rtc, hclk and pclk, * USB controller clocks: AHB slave, I2C, OTG, OHCI and device. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-24clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbolVladimir Zapolskiy
The change adds COMMON_CLK_NXP configuration symbol and enables it for NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp folder for NXP common clock framework drivers other than LPC18XX one. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23Merge tag 'sunxi-clocks-for-4.5' of ↵Michael Turquette
https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next Allwinner clocks changes for 4.5 Clock patches for the Allwinner SoCs: - H3 clocks - A10/A20 Video Engine clocks - DRAM gates - A80 special CPU clock
2015-12-23Merge branch 'clk-rockchip' into clk-nextMichael Turquette
2015-12-23clk: rockchip: rk3036: include downstream muxes into fractional dividersXing Zheng
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported RK3036 SoCs. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: add flag for clocks that need to be enabled on rate changesHeiko Stuebner
Some clocks need to be enabled to accept rate changes. This patch adds a new flag CLK_SET_RATE_UNGATE that lets clk_change_rate enable the clock before trying to change the rate and disable it again afterwards. This of course doesn't effect clocks that are already running at that point, as their refcount will only temporarily increase. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: Allow the RK3288 SPDIF clocks to change their parentSjoerd Simons
The clock branches leading to sclk_spdif and sclk_spdif_8ch on RK3288 SoCs only feed those clocks, allow those clocks to change their parents all the way up the hierarchy. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: include downstream muxes into fractional dividersHeiko Stuebner
Use the newly introduced possibility to combine the fractional dividers with their downstream muxes for all fractional dividers on currently supported Rockchip SoCs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-23clk: rockchip: handle mux dependency of fractional dividersHeiko Stuebner
The fractional dividers of Rockchip SoCs contain an "auto-gating-feature" that requires the downstream mux to actually point to the fractional divider and the fractional divider gate to be enabled, for it to really accept changes to the divider ratio. The downstream muxes themselfs are not generic enough to include them directly into the fractional divider, as they have varying sources of parent clocks including not only clocks related to the fractional dividers but other clocks as well. To solve this, allow our clock branches to specify direct child clock- branches in the new child property, let the fractional divider register its downstream mux through this and add a clock notifier that temporarily switches the mux setting when it notices rate changes to the fractional divider. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22Merge branch 'clk-bcm2835' into clk-nextMichael Turquette
2015-12-22clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.Eric Anholt
There are a pair of SPI masters and a mini UART that were last minute additions. As a result, they didn't get integrated in the same way as the other gates off of the VPU clock in CPRMAN. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22Merge branch 'clk-dove' into clk-nextMichael Turquette
2015-12-22clk: add Dove PLL divider support for GPU, VMeta and AXI clocksRussell King
Add support for the Dove PLL dividers, which are used to generate the clocks for the AXI bus, as well as the GPU and VMeta peripherals. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-22Merge tag 'clk-samsung-4.5' of git://linuxtv.org/snawrocki/samsung into clk-nextMichael Turquette
drivers/clk/samsung updates (mostly bug fixes): - instantiation of the cpu clocks and addition of the GSCL IP parent clocks to the list of available consumer clocks for exynos542x SoCs; - MFC IP parent clock fix for exynos542x; - fix of locking bug in samsung/clk-cpu.c which caused system crashes with cpufreq enabled; - minor cleanup for s3c2410.
2015-12-22Merge commit 'fe5fa8fbd4d47f40a45fa29ee1abdb10cb061ec2' into clk-nextMichael Turquette
2015-12-22Merge tag 'imx-clk-v4.5' of ↵Michael Turquette
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next The i.MX clock updates for 4.5: - Add is_prepared function callback for pllv3 clock driver - Use imx_check_clocks() on imx6ul and imx7d clock drivers to save some code - Add a core clock for imx7d to support generic cpufreq driver - Support imx6q clock routing with OSC to anaclk2/2b - To support more precise pixel clocks on imx5, allow ipu_di_sel clock selectors to influence the PLLs that they are derived from - A cleanup on imx25 OSC clock
2015-12-22Merge tag 'v4.5-rockchip-clk1_1' of ↵Michael Turquette
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Rockchip clock changes for 4.5 containing - a new pll-type used on rk3036 and other Cortex-A7 socs - new clock-trees for rk3036 and rk3228 - switch rk3288 plls to slow mode on reboot - a bunch of new clock ids - some more critical clocks - wrong register offsets for the rk3368 cpuclks - allowing more than 2 parents for the cpuclk
2015-12-22Merge branch 'clk-shmobile-for-v4.5' of ↵Michael Turquette
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
2015-12-22clk: fix codying style of if ... else blocksMasahiro Yamada
This code is unreadable due to the blank line between if and else blocks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2015-12-21clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner
As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") states, switching the PLLs to slow-mode is only necessary when rebooting using the soft-reset done through the CRU. The dwc2 controllers used create really big number of interrupts in special constellations involving usb-hubs and their number is so high, it can even overwhelm the interrupt handler if the cpu-speed os to low. Right now the PLLs are put into slow-mode in a shutdown syscore_ops callback which means it happens on all reboots (not only the soft-reset ones) and even on poweroff actions. This can result in the system not powering off and getting stuck instead, so we should move the slow-mode change nearer to the actual reboot action. For this we introduce the possiblity to also set a callback that gets called from the restart-handler directly prior to restarting the system and move the shutdown-callback to this new option. With this the slow-mode switch is done only on the necessary reboots and also has a smaller possibility of causing artifacts. Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288") Signed-off-by: Heiko Stuebner <heiko.stuebner@collabora.com> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2015-12-17clk: tegra: Read correct IDDQ register in PLL_SS registrationBill Huang
This fixes a bug in tegra_clk_register_pllss() which mistakenly assume the IDDQ register is the PLL base address. Signed-off-by: Bill Huang <bilhuang@nvidia.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: Fix WARN_ON in PLL_RE registrationBill Huang
This fixes two things. - Read the correct IDDQ register - Check the correct IDDQ bit position Signed-off-by: Bill Huang <bilhuang@nvidia.com> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Fix issues with rates for VCO PLLsAndrew Bresticker
Without this change clk_get_rate would return the final output rather than the VCO output as it would factor in the pdiv when it shouldn't. This will cause problems for all dividers in the subtree of the VCO PLL. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: Add support for Tegra210 clocksRhyland Klein
Implement clock support for Tegra210. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: Add Super Gen5 LogicBill Huang
Super clock divider control and clock source mux of Tegra210 has changed a little against prior SoCs, this patch adds Gen5 logic to address those differences. Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add logic for SSBill Huang
Add some logic for Spread Spectrum control. It is used in conjuncture with SDM fractional dividers. SSC has to be disabled when we configure the divider settings. Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add dyn_ramp callbackRhyland Klein
Add a callback to the pll_params for custom dynamic ramping functions which can be specified per PLL. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add Set_default logicBill Huang
Add logic which (if specified for a pll) can verify that a PLL is set to the proper default value and if not can set it. This can be specified per PLL as each will have different default values. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Adjust vco_min if SDM presentBill Huang
This code makes use of the SDM fractional divider if present to constrain the allowable programming range of the PLL divider register bitfields to take advantage of higher frequency granularity that can be induced by the SDM divider. Based on original work by Aleksandr Frid <afrid@nvidia.com> Signed-off-by: Bill Huang <bilhuang@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add support for PLLMB for Tegra210Rhyland Klein
Tegra210 SoC's have 2 PLLs for memory usage. Add plumbing to register and handle PLLMB. PLLMB is used to allow switching between 2 PLLM's without having to use and intermediate backup PLL, as we need to lock the PLL before we can switch to it. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17clk: tegra: pll: Add specialized logic for Tegra210Rhyland Klein
On Tegra210 SoC's, the logic to enable several of the plls is different from previous generations. Therefore, add registration functions specific to Tegra210 which will handle them appropriately. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-16clk: rockchip: rk3036: enable the CLK_IGNORE_UNUSED flag for aclk_vioYakir Yang
ACLK_VIO is the noc bus clock for display module, display cann't read data from ddr without this clock enabled. Due to it shouldn't belong to any driver, but we need it enabled, so just mark it as the CLK_IGNORE_UNUSED flag. Signed-off-by: Yakir Yang <ykk@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-12-16clk: s3c2410: removed unneeded variable in s3c24xx_clkout_set_parentPrasanna Karthik
Remove unneeded variable used to store return value. Signed-off-by: Prasanna Karthik <mkarthi3@visteon.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16clk: exynos: use irqsave version of spin_lock to avoid deadlock with irqsMarek Szyprowski
It is allowed to enable/disable clocks from interrupts, so common Exynos ARM clock management code for CPUfreq should use 'irqsave' version of spin_lock calls to avoid potential deadlock caused by spin_lock recursion. The same spin_lock is used by gate/mux clocks during enable/disable calls. This deadlock, can be reproduced by enabling CPUfreq (ondemand or userspace) and decoding video with s5p-mfc driver. Relevant stack trace: [ 5928.061534] BUG: spinlock recursion on CPU#0, bash/1252 [ 5928.061609] lock: 0xee80454c, .magic: dead4ead, .owner: bash/1252, .owner_cpu: 0 [ 5928.068586] CPU: 0 PID: 1252 Comm: bash Tainted: G W 4.4.0-rc4-00001-g447a7fd #678 [ 5928.077260] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 5928.083359] [<c00153dc>] (unwind_backtrace) from [<c00121b4>] (show_stack+0x10/0x14) [ 5928.091072] [<c00121b4>] (show_stack) from [<c0213e28>] (dump_stack+0x68/0xb8) [ 5928.098275] [<c0213e28>] (dump_stack) from [<c005c1ec>] (do_raw_spin_lock+0x184/0x1ac) [ 5928.106177] [<c005c1ec>] (do_raw_spin_lock) from [<c05cfa98>] (_raw_spin_lock_irqsave+0x20/0x28) [ 5928.114943] [<c05cfa98>] (_raw_spin_lock_irqsave) from [<c0468698>] (clk_gate_endisable+0x24/0x98) [ 5928.123882] [<c0468698>] (clk_gate_endisable) from [<c0464d40>] (clk_core_disable+0x60/0x84) [ 5928.132299] [<c0464d40>] (clk_core_disable) from [<c0465e00>] (clk_disable+0x24/0x30) [ 5928.140117] [<c0465e00>] (clk_disable) from [<c03f3b80>] (s5p_mfc_handle_frame+0x254/0x860) [ 5928.148445] [<c03f3b80>] (s5p_mfc_handle_frame) from [<c03f4b34>] (s5p_mfc_irq+0x890/0xa24) [ 5928.156778] [<c03f4b34>] (s5p_mfc_irq) from [<c00627bc>] (handle_irq_event_percpu+0x50/0x14c) [ 5928.165283] [<c00627bc>] (handle_irq_event_percpu) from [<c00628f0>] (handle_irq_event+0x38/0x5c) [ 5928.174143] [<c00628f0>] (handle_irq_event) from [<c0065864>] (handle_fasteoi_irq+0xdc/0x1a4) [ 5928.182645] [<c0065864>] (handle_fasteoi_irq) from [<c0062090>] (generic_handle_irq+0x18/0x28) [ 5928.191236] [<c0062090>] (generic_handle_irq) from [<c00621a4>] (__handle_domain_irq+0x6c/0xdc) [ 5928.199917] [<c00621a4>] (__handle_domain_irq) from [<c0009470>] (gic_handle_irq+0x4c/0x98) [ 5928.208249] [<c0009470>] (gic_handle_irq) from [<c0012c54>] (__irq_svc+0x54/0x90) [ 5928.215709] Exception stack(0xeddb5cb8 to 0xeddb5d00) [ 5928.220745] 5ca0: ee80454c faddfadc [ 5928.228906] 5cc0: 00000000 01000001 ee831ce0 f8114200 ee807c00 01130520 00000403 eddb5d84 [ 5928.237063] 5ce0: ee807c48 2faf0800 ee807c0c eddb5d08 c046b618 c046b634 20000053 ffffffff [ 5928.245225] [<c0012c54>] (__irq_svc) from [<c046b634>] (exynos_cpuclk_notifier_cb+0x170/0x270) [ 5928.253823] [<c046b634>] (exynos_cpuclk_notifier_cb) from [<c003cb58>] (notifier_call_chain+0x44/0x84) [ 5928.263106] [<c003cb58>] (notifier_call_chain) from [<c003ccd4>] (__srcu_notifier_call_chain+0x6c/0x9c) [ 5928.272480] [<c003ccd4>] (__srcu_notifier_call_chain) from [<c003cd1c>] (srcu_notifier_call_chain+0x18/0x20) [ 5928.282288] [<c003cd1c>] (srcu_notifier_call_chain) from [<c0464ed0>] (__clk_notify+0x6c/0x74) [ 5928.290881] [<c0464ed0>] (__clk_notify) from [<c0465388>] (clk_propagate_rate_change+0xa0/0xac) [ 5928.299561] [<c0465388>] (clk_propagate_rate_change) from [<c0465378>] (clk_propagate_rate_change+0x90/0xac) [ 5928.309370] [<c0465378>] (clk_propagate_rate_change) from [<c04666fc>] (clk_core_set_rate_nolock+0x64/0xa8) [ 5928.319091] [<c04666fc>] (clk_core_set_rate_nolock) from [<c0466760>] (clk_set_rate+0x20/0x30) [ 5928.327686] [<c0466760>] (clk_set_rate) from [<c0428c70>] (set_target+0xe8/0x23c) [ 5928.335152] [<c0428c70>] (set_target) from [<c04244d0>] (__cpufreq_driver_target+0x184/0x29c) [ 5928.343655] [<c04244d0>] (__cpufreq_driver_target) from [<c0427128>] (cpufreq_set+0x44/0x64) [ 5928.352074] [<c0427128>] (cpufreq_set) from [<c0423948>] (store_scaling_setspeed+0x5c/0x74) [ 5928.360407] [<c0423948>] (store_scaling_setspeed) from [<c04238d0>] (store+0x7c/0x98) [ 5928.368221] [<c04238d0>] (store) from [<c0132540>] (sysfs_kf_write+0x44/0x48) [ 5928.375338] [<c0132540>] (sysfs_kf_write) from [<c0131b9c>] (kernfs_fop_write+0xb8/0x1bc) [ 5928.383496] [<c0131b9c>] (kernfs_fop_write) from [<c00d71f8>] (__vfs_write+0x2c/0xd4) [ 5928.391308] [<c00d71f8>] (__vfs_write) from [<c00d7de8>] (vfs_write+0xa0/0x144) [ 5928.398598] [<c00d7de8>] (vfs_write) from [<c00d8048>] (SyS_write+0x44/0x84) [ 5928.405631] [<c00d8048>] (SyS_write) from [<c000f540>] (ret_fast_syscall+0x0/0x3c) CC: stable@vger.kernel.org # v4.2+ Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16clk: samsung: exynos542x: fix MFC clock hierarchy parentMarek Szyprowski
Proper source for MFC block is mout_user_aclk333 (in datasheet named USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-12-16clk: samsung: exynos542x/5800: fix cpu clock configuration dataBartlomiej Zolnierkiewicz
Fix cpu clock configuration data for Exynos5422/5800 SoCs (they use higher PCLK_DBG divider values than Exynos5420 and support additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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