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2013-08-13clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocksSylwester Nawrocki
The ISP clock registers belong to the ISP power domain and may change their values if this power domain is switched off/on. Add CLK_GET_RATE_NOCACHE flags to ensure we do not rely on invalid cached data when setting or getting frequency of those clocks. Without this fix the FIMC-IS Cortex-A5 core and AXI bus clocks have incorrect frequencies, which breaks the ISP operation and starting the video pipeline fails with timeouts reported by the FIMC-IS firmware. See related commit 722a860ecb29aa34ec6f7d7f32b949209e8 "[media] exynos4-is: Fix FIMC-IS clocks initialization" for more details. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-13clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxesSoren Brinkmann
Zynq's Ethernet clocks are created by the following hierarchy: mux0 ---> div0 ---> div1 ---> mux1 ---> gate Rate change requests on the gate have to propagate all the way up to div0 to properly leverage all dividers. Mux1 was missing the CLK_SET_RATE_PARENT flag, which is required to achieve this. This does not fix a specific regression but the clock driver was merged for 3.11-rc1, so best to fix the known bugs before the release. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added to changelog]
2013-08-13clk/zynq/clkc: Add dedicated spinlock for the SWDTSoren Brinkmann
The clk_mux for the system watchdog timer reused the register lock dedicated to the Ethernet module - for no apparent reason. Add a lock dedicated to the SWDT's clock register to remove this wrong dependency. This does not fix a specific regression but the clock driver was merged for 3.11-rc1, so best to fix the known bugs before the release. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: added to changelog]
2013-07-03Merge tag 'pm+acpi-3.11-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management and ACPI updates from Rafael Wysocki: "This time the total number of ACPI commits is slightly greater than the number of cpufreq commits, but Viresh Kumar (who works on cpufreq) remains the most active patch submitter. To me, the most significant change is the addition of offline/online device operations to the driver core (with the Greg's blessing) and the related modifications of the ACPI core hotplug code. Next are the freezer updates from Colin Cross that should make the freezing of tasks a bit less heavy weight. We also have a couple of regression fixes, a number of fixes for issues that have not been identified as regressions, two new drivers and a bunch of cleanups all over. Highlights: - Hotplug changes to support graceful hot-removal failures. It sometimes is necessary to fail device hot-removal operations gracefully if they cannot be carried out completely. For example, if memory from a memory module being hot-removed has been allocated for the kernel's own use and cannot be moved elsewhere, it's desirable to fail the hot-removal operation in a graceful way rather than to crash the kernel, but currenty a success or a kernel crash are the only possible outcomes of an attempted memory hot-removal. Needless to say, that is not a very attractive alternative and it had to be addressed. However, in order to make it work for memory, I first had to make it work for CPUs and for this purpose I needed to modify the ACPI processor driver. It's been split into two parts, a resident one handling the low-level initialization/cleanup and a modular one playing the actual driver's role (but it binds to the CPU system device objects rather than to the ACPI device objects representing processors). That's been sort of like a live brain surgery on a patient who's riding a bike. So this is a little scary, but since we found and fixed a couple of regressions it caused to happen during the early linux-next testing (a month ago), nobody has complained. As a bonus we remove some duplicated ACPI hotplug code, because the ACPI-based CPU hotplug is now going to use the common ACPI hotplug code. - Lighter weight freezing of tasks. These changes from Colin Cross and Mandeep Singh Baines are targeted at making the freezing of tasks a bit less heavy weight operation. They reduce the number of tasks woken up every time during the freezing, by using the observation that the freezer simply doesn't need to wake up some of them and wait for them all to call refrigerator(). The time needed for the freezer to decide to report a failure is reduced too. Also reintroduced is the check causing a lockdep warining to trigger when try_to_freeze() is called with locks held (which is generally unsafe and shouldn't happen). - cpufreq updates First off, a commit from Srivatsa S Bhat fixes a resume regression introduced during the 3.10 cycle causing some cpufreq sysfs attributes to return wrong values to user space after resume. The fix is kind of fresh, but also it's pretty obvious once Srivatsa has identified the root cause. Second, we have a new freqdomain_cpus sysfs attribute for the acpi-cpufreq driver to provide information previously available via related_cpus. From Lan Tianyu. Finally, we fix a number of issues, mostly related to the CPUFREQ_POSTCHANGE notifier and cpufreq Kconfig options and clean up some code. The majority of changes from Viresh Kumar with bits from Jacob Shin, Heiko Stübner, Xiaoguang Chen, Ezequiel Garcia, Arnd Bergmann, and Tang Yuantian. - ACPICA update A usual bunch of updates from the ACPICA upstream. During the 3.4 cycle we introduced support for ACPI 5 extended sleep registers, but they are only supposed to be used if the HW-reduced mode bit is set in the FADT flags and the code attempted to use them without checking that bit. That caused suspend/resume regressions to happen on some systems. Fix from Lv Zheng causes those registers to be used only if the HW-reduced mode bit is set. Apart from this some other ACPICA bugs are fixed and code cleanups are made by Bob Moore, Tomasz Nowicki, Lv Zheng, Chao Guan, and Zhang Rui. - cpuidle updates New driver for Xilinx Zynq processors is added by Michal Simek. Multidriver support simplification, addition of some missing kerneldoc comments and Kconfig-related fixes come from Daniel Lezcano. - ACPI power management updates Changes to make suspend/resume work correctly in Xen guests from Konrad Rzeszutek Wilk, sparse warning fix from Fengguang Wu and cleanups and fixes of the ACPI device power state selection routine. - ACPI documentation updates Some previously missing pieces of ACPI documentation are added by Lv Zheng and Aaron Lu (hopefully, that will help people to uderstand how the ACPI subsystem works) and one outdated doc is updated by Hanjun Guo. - Assorted ACPI updates We finally nailed down the IA-64 issue that was the reason for reverting commit 9f29ab11ddbf ("ACPI / scan: do not match drivers against objects having scan handlers"), so we can fix it and move the ACPI scan handler check added to the ACPI video driver back to the core. A mechanism for adding CMOS RTC address space handlers is introduced by Lan Tianyu to allow some EC-related breakage to be fixed on some systems. A spec-compliant implementation of acpi_os_get_timer() is added by Mika Westerberg. The evaluation of _STA is added to do_acpi_find_child() to avoid situations in which a pointer to a disabled device object is returned instead of an enabled one with the same _ADR value. From Jeff Wu. Intel BayTrail PCH (Platform Controller Hub) support is added to the ACPI driver for Intel Low-Power Subsystems (LPSS) and that driver is modified to work around a couple of known BIOS issues. Changes from Mika Westerberg and Heikki Krogerus. The EC driver is fixed by Vasiliy Kulikov to use get_user() and put_user() instead of dereferencing user space pointers blindly. Code cleanups are made by Bjorn Helgaas, Nicholas Mazzuca and Toshi Kani. - Assorted power management updates The "runtime idle" helper routine is changed to take the return values of the callbacks executed by it into account and to call rpm_suspend() if they return 0, which allows us to reduce the overall code bloat a bit (by dropping some code that's not necessary any more after that modification). The runtime PM documentation is updated by Alan Stern (to reflect the "runtime idle" behavior change). New trace points for PM QoS are added by Sahara (<keun-o.park@windriver.com>). PM QoS documentation is updated by Lan Tianyu. Code cleanups are made and minor issues are addressed by Bernie Thompson, Bjorn Helgaas, Julius Werner, and Shuah Khan. - devfreq updates New driver for the Exynos5-bus device from Abhilash Kesavan. Minor cleanups, fixes and MAINTAINERS update from MyungJoo Ham, Abhilash Kesavan, Paul Bolle, Rajagopal Venkat, and Wei Yongjun. - OMAP power management updates Adaptive Voltage Scaling (AVS) SmartReflex voltage control driver updates from Andrii Tseglytskyi and Nishanth Menon." * tag 'pm+acpi-3.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (162 commits) cpufreq: Fix cpufreq regression after suspend/resume ACPI / PM: Fix possible NULL pointer deref in acpi_pm_device_sleep_state() PM / Sleep: Warn about system time after resume with pm_trace cpufreq: don't leave stale policy pointer in cdbs->cur_policy acpi-cpufreq: Add new sysfs attribute freqdomain_cpus cpufreq: make sure frequency transitions are serialized ACPI: implement acpi_os_get_timer() according the spec ACPI / EC: Add HP Folio 13 to ec_dmi_table in order to skip DSDT scan ACPI: Add CMOS RTC Operation Region handler support ACPI / processor: Drop unused variable from processor_perflib.c cpufreq: tegra: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: s3c64xx: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: omap: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: imx6q: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: exynos: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: dbx500: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: davinci: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: arm-big-little: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: powernow-k8: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: pcc: call CPUFREQ_POSTCHANGE notfier in error cases ...
2013-07-03Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds
Pull clock framework updates from Mike Turquette: "The common clock framework changes for 3.11 include new clock drivers across several different platforms and architectures, fixes to existing drivers, a MAINTAINERS file fix and improvements to the basic clock types that allow them to be of use to more platforms than before. Only a few fixes to the core framework are included with most all of the changes landing in the various clock drivers themselves." * tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux: (55 commits) clk: tegra: fix ifdef for tegra_periph_reset_assert inline clk: tegra: provide tegra_periph_reset_assert alternative clk: exynos4: Fix clock aliases for cpufreq related clocks clk: samsung: Add MUX_FA macro to pass flag and alias clk: add support for Rockchip gate clocks clk: vexpress: Make the clock drivers directly available for arm64 clk: vexpress: Use full node name to identify individual clocks clk: tegra: T114: add DFLL DVCO reset control clk: tegra: T114: add DFLL source clocks clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL clk: gate: add CLK_GATE_HIWORD_MASK clk: divider: add CLK_DIVIDER_HIWORD_MASK flag clk: mux: add CLK_MUX_HIWORD_MASK clk: Always notify whole subtree when reparenting MAINTAINERS: make drivers/clk entry match subdirs clk: honor CLK_GET_RATE_NOCACHE in clk_set_rate clk: use clk_get_rate() for debugfs clk: tegra: Use override bits when needed clk: tegra: override bits for Tegra30 PLLM clk: tegra: override bits for Tegra114 PLLM ...
2013-07-02Merge tag 'late-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late changes from Arnd Bergmann: "These are changes that arrived a little late before the merge window or that have multiple dependencies on previous branches so they did not fit into one of the earlier ones. There are 10 branches merged here, a total of 39 non-merge commits. Contents are a mixed bag for the above reasons: * Two new SoC platforms: ST microelectronics stixxxx and the TI 'Nspire' graphing calculator. These should have been in the 'soc' branch but were a little late * Support for the Exynos 5420 variant in mach-exynos, which is based on the other exynos branches to avoid conflicts. * Various small changes for sh-mobile, ux500 and davinci * Common clk support for MSM" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits) ARM: ux500: bail out on alien cpus ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins serial: sh-sci: Initialise variables before access in sci_set_termios() ARM: stih41x: Add B2020 board support ARM: stih41x: Add B2000 board support ARM: sti: Add DEBUG_LL console support ARM: sti: Add STiH416 SOC support ARM: sti: Add STiH415 SOC support ARM: msm: Migrate to common clock framework ARM: msm: Make proc_comm clock control into a platform driver ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver ARM: msm: Remove clock-7x30.h include file ARM: msm: Remove custom clk_set_{max,min}_rate() API ARM: msm: Remove custom clk_set_flags() API msm: iommu: Use clk_set_rate() instead of clk_set_min_rate() msm: iommu: Convert to clk_prepare/unprepare msm_sdcc: Convert to clk_prepare/unprepare usb: otg: msm: Convert to clk_prepare/unprepare msm_serial: Use devm_clk_get() and properly return errors msm_serial: Convert to clk_prepare/unprepare ...
2013-07-02Merge tag 'drivers-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver specific changes from Arnd Bergmann: "These changes are all driver specific and cross over between arm-soc contents and some other subsystem, in these cases cpufreq, crypto, dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have these changes merged through arm-soc. As we proceed to untangle the dependencies between platform code and driver code, the amount of changes in this category is fortunately shrinking, for 3.11 we have 16 branches here and 101 non-merge changesets, the majority of which are for the stedma40 dma engine driver used in the ux500 platform. Cleaning up that code touches multiple subsystems, but gets rid of the dependency in the end. The mailbox code moved out from mach-omap2 to drivers/mailbox is an intermediate step and is still omap specific at the moment. Patches exist to generalize the subsystem and add other drivers with the same API, but those did not make it for 3.11." * tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits) crypto: ux500: use dmaengine_submit API crypto: ux500: use dmaengine_prep_slave_sg API crypto: ux500: use dmaengine_device_control API crypto: ux500/crypt: add missing __iomem qualifiers crypto: ux500/hash: add missing static qualifiers crypto: ux500/hash: use readl on iomem addresses dmaengine: ste_dma40: Declare memcpy config as static ARM: ux500: Remove mop500_snowball_ethernet_clock_enable() ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO ARM: ux500: Provide a AB8500 GPIO Device Tree node gpio: rcar: fix gpio_rcar_of_table gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections gpio-rcar: Reference core gpio documentation in the DT bindings clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2 ARM: dts: Update Samsung I2S documentation ARM: dts: add clock provider information for i2s controllers in Exynos5250 ARM: dts: add Exynos audio subsystem clock controller node clk: samsung: register audio subsystem clocks using common clock framework ARM: dts: use #include for all device trees for Samsung pinctrl: s3c24xx: use correct header for chained_irq functions ...
2013-07-02Merge tag 'dt-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC device tree changes from Arnd Bergmann: "These changes from 30 individual branches for the most part update device tree files, but there are also a few source code changes that have crept in this time, usually in order to atomically move over a driver from using hardcoded data to DT probing. A number of platforms change their DT files to use the C preprocessor, which is causing a bit of churn, but that is hopefully only this once" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits) ARM: at91: dt: rm9200ek: add spi support ARM: at91: dt: rm9200: add spi support ARM: at91/DT: at91sam9n12: add SPI DMA client infos ARM: at91/DT: sama5d3: add SPI DMA client infos ARM: at91/DT: fix SPI compatibility string ARM: Kirkwood: Fix the internal register ranges translation ARM: dts: bcm281xx: change comment to C89 style ARM: mmc: bcm281xx SDHCI driver (dt mods) ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency ARM: dts: omap4-panda: Fix DVI EDID reads ARM: dts: omap4-panda: Add USB Host support arm: mvebu: enable mini-PCIe connectors on Armada 370 RD ARM: shmobile: irqpin: add a DT property to enable masking on parent ARM: dts: AM43x EPOS EVM support ARM: dts: OMAP5: Add bandgap DT entry ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone ...
2013-07-02Merge tag 'soc-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC specific changes from Arnd Bergmann: "These changes are all to SoC-specific code, a total of 33 branches on 17 platforms were pulled into this. Like last time, Renesas sh-mobile is now the platform with the most changes, followed by OMAP and EXYNOS. Two new platforms, TI Keystone and Rockchips RK3xxx are added in this branch, both containing almost no platform specific code at all, since they are using generic subsystem interfaces for clocks, pinctrl, interrupts etc. The device drivers are getting merged through the respective subsystem maintainer trees. One more SoC (u300) is now multiplatform capable and several others (shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving towards that goal with this series but need more work. Also noteworthy is the work on PCI here, which is traditionally part of the SoC specific code. With the changes done by Thomas Petazzoni, we can now more easily have PCI host controller drivers as loadable modules and keep them separate from the platform code in drivers/pci/host. This has already led to the discovery that three platforms (exynos, spear and imx) are actually using an identical PCIe host controller and will be able to share a driver once support for spear and imx is added." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits) ARM: integrator: let pciv3 use mem/premem from device tree ARM: integrator: set local side PCI addresses right ARM: dts: Add pcie controller node for exynos5440-ssdk5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC ARM: EXYNOS: Enable PCIe support for Exynos5440 pci: Add PCIe driver for Samsung Exynos ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data ARM: keystone: Move CPU bringup code to dedicated asm file ARM: multiplatform: always pick one CPU type ARM: imx: select syscon for IMX6SL ARM: keystone: select ARM_ERRATA_798181 only for SMP ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1 ARM: OMAP2+: AM43x: resolve SMP related build error dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs ...
2013-07-02Merge tag 'fixes-non-critical-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-cricitical bug fixes from Arnd Bergmann: "These are various bug fixes that were not considered important enough for merging into 3.10. The majority of the ARM fixes are for the OMAP and at91 platforms, and there is another set of bug fixes for device drivers that resolve 'randconfig' build errors and that the subsystem maintainers either did not pick up or preferred to get merged through the arm-soc tree." * tag 'fixes-non-critical-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits) ARM: at91/PMC: use at91_usb_rate() for UTMI PLL ARM: at91/PMC: fix at91sam9n12 USB FS init ARM: at91/PMC: at91sam9n12 family has a PLLB ARM: at91/PMC: sama5d3 family doesn't have a PLLB ARM: tegra: fix section mismatch in tegra_pmc_parse_dt ARM: mxs: don't select HAVE_PWM ARM: mxs: stub out mxs_pm_init for !CONFIG_PM cpuidle: calxeda: select ARM_CPU_SUSPEND ARM: mvebu: fix length of ethernet registers in mv78260 dtsi ARM: at91: cpuidle: Fix target_residency ARM: at91: fix at91_extern_irq usage for non-dt boards ARM: sirf: use CONFIG_SIRF rather than CONFIG_PRIMA2 where necessary clocksource: kona: adapt to CLOCKSOURCE_OF_DECLARE change X.509: do not emit any informational output mtd: omap2: allow bulding as a module [SCSI] nsp32: use mdelay instead of large udelay constants hwrng: bcm2835: fix MODULE_LICENSE tag ARM: at91: Change the internal SRAM memory type MT_MEMORY_NONCACHED ARM: at91: Fix link breakage when !CONFIG_PHYLIB MAINTAINERS: Add exynos filename match to ARM/S5P EXYNOS ARM ARCHITECTURES ...
2013-06-28Merge branch 'acpi-lpss'Rafael J. Wysocki
* acpi-lpss: ACPI / LPSS: override SDIO private register space size from ACPI tables ACPI / LPSS: mask the UART TX completion interrupt ACPI / LPSS: add support for Intel BayTrail Conflicts: drivers/acpi/acpi_lpss.c (with commit b9e95fc)
2013-06-22clk: exynos4: Fix clock aliases for cpufreq related clocksTushar Behera
cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. Clock alias modifications for EXYNOS4 specific clocks are as below. Alias for clock 'arm_clk' is 'armclk'. Alias for clock 'mout_apll' is 'mout_apll'. Alias for clock 'mout_core' is 'moutcore'. For EXYNOS4210, alias for clock 'sclk_mpll' is 'mout_mpll'. For EXYNOS4412, alias for clock 'mout_mpll_user_c' is 'mout_mpll'. Some of the clock aliases are newly defined and some are fixed up. While at it, also modify the debug messages to print the clock values appropriately. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-22clk: samsung: Add MUX_FA macro to pass flag and aliasTushar Behera
Cpufreq driver for some Samsung platforms have not yet been designed as a platform driver, thereby they can only access clocks with an alias name. For EXYNOS4210, one such clock also requires a flag to be set, hence there is a need to create another macro that can handle both flag and alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-20clk: add support for Rockchip gate clocksHeiko Stübner
This adds basic support for gate-clocks on Rockchip SoCs. There are 16 gates in each register and use the HIWORD_MASK mechanism for changing gate settings. The gate registers form a continuos block which makes the dt node structure a matter of taste, as either all 160 gates can be put into one gate clock spanning all registers or they can be divided into the 10 individual gates containing 16 clocks each. The code supports both approaches. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-20Merge tag 'nomadik-dt-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt From Linus Walleij: Nomadik DT and clock work: - Lee Jones' pinctrl compat ontology patches - A real clock driver for the Nomadik, 100% DT-based - Device tree changes for the Nomadik clocks * tag 'nomadik-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: nomadik: add the new clocks to the device tree clk: nomadik: implement the Nomadik clocks properly pinctrl/nomadik: Standardise Pinctrl compat string for Nomadik based platforms ARM: nomadik: Standardise Nomadik STN8815 based Pinctrl compat string in the DTS Conflicts: arch/arm/boot/dts/ste-nomadik-s8815.dts Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-20clk: nomadik: implement the Nomadik clocks properlyLinus Walleij
The Nomadik clock implementation was a stub just using fixed clocks. This implements the clocks properly instead of relying on them all being on at boot and leaving them all on. The PLLs are on the top locking to the main chrystal oscillator, then the HCLK for the peripherals are below PLL2. The gated clocks are implemented with zero cells and given the clock ID as a property of each node, so every gate need to have its own node in the device tree. This is because the gate registers contain both HCLK gates and PCLK gates, where the latter has HCLK as parent. As can be seen from the register layout, this is a complete mixup, which means all these gates need their own node to properly model parent/child relations for PCLKs apart from the HCLKs. This driver also adds a helpful debugfs file to inspect the hardware state of the clock gates. This is the end result in <debugfs>/clk/clk_summary after applying a proper device tree: ulpiclk 0 0 60000000 mxtal 3 3 19200000 pll2 1 1 864000000 clk48 3 3 48000000 rngcclk 1 1 48000000 usbmclk 0 0 48000000 mshcclk 0 0 48000000 mspclk3 0 0 48000000 x3dclk 0 0 48000000 skeclk 0 0 48000000 owmclk 0 0 48000000 mspclk2 0 0 48000000 mspclk1 0 0 48000000 uart2clk 0 0 48000000 ipbmcclk 0 0 48000000 ipi2cclk 0 0 48000000 usbclk 0 0 48000000 mspclk0 0 0 48000000 uart1clk 1 2 48000000 i2c1clk 0 0 48000000 i2c0clk 0 0 48000000 sdiclk 1 1 48000000 uart0clk 0 0 48000000 sspiclk 0 0 48000000 irdaclk 0 0 48000000 clk72 0 0 72000000 difclk 0 0 72000000 clcdclk 0 0 72000000 clk216 0 0 216000000 hsiclkrx 0 0 216000000 clk108 0 0 108000000 hsiclktx 0 0 108000000 clk27 0 0 27000000 pll1 1 1 264000000 hclk 3 3 264000000 hclkrng 1 1 264000000 hclkusbm 0 0 264000000 hclkcryp 0 0 264000000 hclkhash 0 0 264000000 hclk3d 0 0 264000000 hclkhpi 0 0 264000000 hclksva 0 0 264000000 hclksaa 0 0 264000000 hclkdif 0 0 264000000 hclkusb 0 0 264000000 hclkclcd 0 0 264000000 hclkdma1 0 0 264000000 hclksdram 0 0 264000000 hclksmc 1 1 264000000 hclkdma0 0 0 264000000 pclk 7 9 264000000 pclkmsp3 0 0 264000000 pclkmshc 0 0 264000000 pclkhsem 0 0 264000000 pclkske 0 0 264000000 pclkowm 0 0 264000000 pclkmsp2 0 0 264000000 pclkmsp1 0 0 264000000 pclkuart2 0 0 264000000 pclkxti 0 0 264000000 pclkhsi 0 0 264000000 pclkmsp0 0 0 264000000 pclkuart1 1 1 264000000 pclki2c1 0 0 264000000 pclki2c0 0 0 264000000 pclksdi 1 1 264000000 pclkuart0 1 1 264000000 pclkssp 0 0 264000000 pclkirda 0 0 264000000 timclk 1 1 2400000 Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-20clk: vexpress: Make the clock drivers directly available for arm64Pawel Moll
The new arm64 architecture has no idea of platform or machine, so it doesn't have to define ARCH_VEXPRESS configuration option at all. To allow user to select the drivers at all, make it depend on ARM64 as well. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-20clk: vexpress: Use full node name to identify individual clocksPawel Moll
Previously all the clocks were reported as "osc". Now it will be something like "/dcc/osc@0". Signed-off-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-20Merge tag 'u300-multiplatform' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc From Linus Walleij: Device Tree and Multiplatform support for U300: - Add devicetree support to timer, pinctrl (probe), I2C block, watchdog, DMA controller and clocks. - Piecewise add a device tree containing all peripherals. - Delete the ATAG boot path. - Delete redundant platform data and board files. - Convert to multiplatform. * tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (40 commits) ARM: u300: switch to using syscon regmap for board ARM: u300: Update MMC configs for u300 defconfig spi: pl022: use DMA by default when probing from DT pinctrl: get rid of all platform data for coh901 ARM: u300: convert MMC/SD clock to device tree ARM: u300: move the gated system controller clocks to DT i2c: stu300: do not request a specific clock name clk: move the U300 fixed and fixed-factor to DT ARM: u300: remove register definition file ARM: u300: add syscon node ARM: u300 use module_spi_driver to register driver ARM: u300: delete remnant machine headers ARM: u300: convert to multiplatform ARM: u300: localize <mach/u300-regs.h> ARM: u300: delete <mach/irqs.h> ARM: u300: delete <mach/hardware.h> ARM: u300: push down syscon registers ARM: u300: remove deps from debug macro ARM: u300: move debugmacro to debug includes ARM: u300: delete all static board data ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-20Merge tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx into next/dtArnd Bergmann
From Michal Simek: arm: Xilinx Zynq dt changes for v3.11 The branch contains: - DT uart handling cleanup - Support for zc706 and zed board - Removal of board compatible string * tag 'zynq-dt-for-3.11' of git://git.xilinx.com/linux-xlnx: arm: dt: zynq: Add support for the zed platform arm: dt: zynq: Add support for the zc706 platform arm: dt: zynq: Use 'status' property for UART nodes arm: zynq: Remove board specific compatibility string clk: zynq: Remove deprecated clock code arm: zynq: Migrate platform to clock controller clk: zynq: Add clock controller driver clk: zynq: Factor out PLL driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-20ARM: sirf: use CONFIG_SIRF rather than CONFIG_PRIMA2 where necessaryArnd Bergmann
I got a build error today that made me realize that it is not possible to build a kernel for a SiRF platform without enabling CONFIG_PRIMA2, since a lot of common code depends on CONFIG_PRIMA2. This fixes all occurences that appear like common SiRF code. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Mark Brown <broonie@linaro.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Barry Song <Baohua.Song@csr.com> Acked-by: Mike Turquette <mturquette@linaro.org>
2013-06-19ACPI / LPSS: add support for Intel BayTrailMika Westerberg
Intel BayTrail has almost the same Low Power Subsystem than Lynxpoint with few differences. Peripherals are clocked with different speeds (typically lower) and the clock is not always gated. To support this we add possibility to share a common fixed rate clock and make clock gating optional. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-06-19clk: exynos5420: register clocks using common clock frameworkChander Kashyap
The EXYNOS5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-18clk: tegra: T114: add DFLL DVCO reset controlPaul Walmsley
Add DFLL DVCO reset line control functions to the CAR IP block driver. The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP block will complete. Thanks to Aleksandr Frid <afrid@nvidia.com> for identifying this and saving hours of debugging time. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-18clk: tegra: T114: add DFLL source clocksPaul Walmsley
Add the input clocks needed by the DFLL IP blocks. Initialize them to 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source. This patch is a collaboration with Peter De Schrijver <pdeschrijver@nvidia.com>. Thanks to Laxman Dewangan <ldewangan@nvidia.com> for identifying the requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout issues. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Andrew Chew <achew@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-19clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2Padmavathi Venna
This patch adds enum entries for div_i2s1 and div_i2s2 which are required for i2s1 and i2s2 controllers. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19clk: samsung: register audio subsystem clocks using common clock frameworkPadmavathi Venna
Audio subsystem is introduced in s5pv210 and exynos platforms. This has seperate clock controller which can control i2s0 and pcm0 clocks. This patch registers the audio subsystem clocks with the common clock framework on Exynos family. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-18clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLLPaul Walmsley
Add clock functions to initialize, enable, and disable the FCPU clock shapers, based on the FCPU voltage rail state. These will be used by the DFLL clocksource driver code. This version of the patch contains a fix for a problem noticed by Andrew Chew <achew@nvidia.com>, where some of the FINETRIM_R bitfields were incorrectly defined. Based on code originally written by Aleksandr Frid <afrid@nvidia.com>. Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com> Cc: Andrew Chew <achew@nvidia.com> Reviewed-by: Andrew Chew <achew@nvidia.com> Cc: Matthew Longnecker <mlongnecker@nvidia.com> Cc: Aleksandr Frid <afrid@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-17ARM: u300: convert MMC/SD clock to device treeLinus Walleij
This converts the last of the U300 clocks to being probed from the device tree. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-17ARM: u300: move the gated system controller clocks to DTLinus Walleij
This moves the slow, fast, AHB bridge and "rest" clocks on the U300 system controller over to registration from the device tree. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-17clk: move the U300 fixed and fixed-factor to DTLinus Walleij
This converts the fixed and fixed-factor clocks in the U300 platform to register themselves from the device tree. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-17ARM: u300: push down syscon registersLinus Walleij
Get rid of the <mach/syscon.h> header as a prerequisite for multiplatform support. Do this by pushing the registers down to their respective drivers and deleting the unused remainder. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16ARM: tegra30: clocks: Fix pciex clock registrationJay Agarwal
Registering pciex as peripheral clock instead of fixed clock as tegra_perih_reset_assert(deassert) api of this clock api gives warning and ultimately does not succeed to assert(deassert) Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: gate: add CLK_GATE_HIWORD_MASKHaojian Zhuang
In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: divider: add CLK_DIVIDER_HIWORD_MASK flagHaojian Zhuang
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: mux: add CLK_MUX_HIWORD_MASKHaojian Zhuang
In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-15clk: Always notify whole subtree when reparentingSoren Brinkmann
A clock's notifier count only reflects notifiers which are registered directly for that clock. A reparent operation though affects the whole subtree because of a potential rate change. When issuing the pre rate change notifications only the notifier count for the clock to be changed is considered and notifiers for subclocks may never be called. Resulting in clocks in the subtree which have registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE notification, without a PRE_RATE_CHANGE_NOTIFICATION. Therefore always traverse the whole subtree when issueing pre rate change notifications during a reparent operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-14Merge tag 'tegra-for-3.11-soc' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc From Stephen Warren: ARM: tegra: core SoC support enhancements This branch contains fixes and enhancement for core Tegra Soc support: * CPU hotplug support for Tegra114. * Some preliminary work on Tegra114 CPU sleep modes. * Minor fix for EMC table DT parsing. * tag 'tegra-for-3.11-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2 ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func ARM: tegra: hook tegra_tear_down_cpu function in the PM suspend init function ARM: tegra: cpuidle: move the init function behind the suspend init function ARM: tegra: remove ifdef in the tegra_resume ARM: tegra: add cpu_disable for hotplug ARM: tegra114: add CPU hotplug support clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops ARM: tegra114: add power up sequence for warm boot CPU ARM: tegra: make tegra_resume can work for Tegra114 ARM: tegra: skip SCU and PL310 code when CPU is not Cortex-A9 ARM: tegra: add an assembly marco to check Tegra SoC ID ARM: tegra: emc: correction of ram-code parsing from dt Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-12Merge tag 'exynos-dt-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt From Kukjin Kim: Update exynos DT for - usb3phy and dwc3 for exynos5250 - keypad for exynos4412 - TMU clock for exynos4210 - MFC clock for exynos4 - DP controller for exynos5250 - G2D clock for exynos4 - some exynos boards * tag 'exynos-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (456 commits) ARM: dts: add ohci and ehci controller nodes for EXYNOS5440 ARM: dts: Update G2D documentation for clock entries ARM: dts: Add clock entries to G2D node for exynos4x12 ARM: dts: Add clock entries to G2D node for exynos4210 ARM: dts: Remove duplicate and add missing G2D nodes clk: exynos4: Add additional G2D clocks ARM: dts: Document DP clock in samsung,exynos5-dp binding ARM: dts: add pin state information for DP HPD support to Exynos5250 ARM: dts: add dts node for the ahci sata exynos5440 ARM: dts: add vmmc regulator support for ODROID-X ARM: dts: add max77686 node entry for ODROID-X ARM: dts: Enable RTC by default on EXYNOS5440 ARM: dts: Add display timing node to exynos5250-arndale.dts ARM: dts: Add clock provider information for DP controller in Exynos5250 SoC ARM: dts: Add DT node for DP controller for Arndale Board ARM: dts: Remove combiner IRQ node from exynos4x12.dtsi ARM: dts: add max8997 device node for exynos4210-origen board ARM: dts: Enable TMU on Origen4210 board ARM: dts: Add TMU clock entries to exynos4210.dtsi ARM: dts: Update MFC documentation for clock entries ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-11clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clockTushar Behera
Currently 'pmu' clock is not handled by any of the drivers. Also before the introduction of CCF, this clock was not defined, hence was left enabled always. When this clock is disabled, software reset register becomes inaccessible and system reboot doesn't work. Upon restoring the default behaviour, system reboot starts working. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: honor CLK_GET_RATE_NOCACHE in clk_set_ratePeter De Schrijver
clk_set_rate() uses clk->rate directly. This causes problems if the clock is marked as CLK_GET_RATE_NOCACHE. Hence call clk_get_rate() to get the current rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: use clk_get_rate() for debugfsPeter De Schrijver
debugfs uses the rate field directly. However this ignores the CLK_GET_RATE_NOCACHE flag. Call clk_get_rate() instead. Tested-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: Use override bits when neededPeter De Schrijver
PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE is set. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: override bits for Tegra30 PLLMPeter De Schrijver
Define override bits for Tegra30 PLLM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: override bits for Tegra114 PLLMPeter De Schrijver
Define override bits for Tegra114 PLLM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge conflict]
2013-06-11clk: tegra: Add fields for override bitsPeter De Schrijver
PLLM can have override bits in the PMC. Describe those in the PLL parameters. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: fix sclk_parentsPeter De Schrijver
Use the correct parents for sclk according to the TRM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: fix pllre initilizationPeter De Schrijver
The PLLRE flags weren't set correctly. Fixed in this patch. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: PLL m,n,p init for Tegra114Peter De Schrijver
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-06-11clk: tegra: allow PLL m,n,p init from SoC filesPeter De Schrijver
The m,n,p fields don't have the same bit offset and width across all PLLs. This patch allows SoC specific files to indicate the offset and width. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>