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2017-08-02Merge tag 'sunxi-clk-fixes-for-4.13' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Pull one Allwinner clock fix from Chen-Yu Tsai: One critical clock fix for sun5i (A10s/A13/R8) which enables propagation of clock rate changes from the "cpu" clock to it's parent PLL clock. This fixes cpufreq related crashes that have been observed on KernelCI with the C.H.I.P. and multi_v7_defconfig. * tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock
2017-08-02Merge tag 'meson-clk-fixes-for-4.13-rc4-v2' of ↵Stephen Boyd
git://github.com/baylibre/clk-meson into clk-fixes Pull one Meson clock fix from Neil Armstrong * tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson: clk: meson: mpll: fix mpll0 fractional part ignored
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet
mpll0 clock is special compared to the other mplls. It needs another bit (ssen) to be set to activate the fractional part the mpll divider Fixes: 007e6e5c5f01 ("clk: meson: mpll: add rw operation") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-07-31clk: samsung: exynos5420: The EPLL rate table correctionsSylwester Nawrocki
This patch fixes values of the EPLL K coefficient and changes the EPLL output frequency values to match exactly what is possible to achieve with given M, P, S, K coefficients. This allows to avoid rounding errors and unexpected frequency being set with clk_set_rate(), due to recalc_rate returning different values than the PLL rate specified in the exynos5420_epll_24mhz_tbl table. E.g. this prevents a case where two consecutive clk_set_rate() calls with same argument result in different PLL output frequency. The PLL output frequencies have been calculated with formula: f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16 where fxtal = 24000000. Fixes: 9842452acd ("clk: samsung: exynos542x: Add EPLL rate table") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-24clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clockMaxime Ripard
The current CPU clock is missing the option to change the rate of its parents, leading to improper rates calculated by cpufreq, and eventually crashes. Cc: <stable@vger.kernel.org> Fixes: 5e73761786d6 ("clk: sunxi-ng: Add sun5i CCU driver") Reported-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-07-18clk: x86: Do not gate clocks enabled by the firmwareCarlo Caione
Read the enable register to determine if the clock is already in use by the firmware. In this case avoid gating the clock. Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Darren Hart (VMware) <dvhart@infradead.org> Signed-off-by: Carlo Caione <carlo@endlessm.com> Fixes: 282a4e4ce5f9 ("platform/x86: Enable Atom PMC platform clocks") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-17clk: gemini: Fix reset regressionLinus Walleij
commit e2860e1f62f2 ("serial: 8250_of: Add reset support") introduced reset support for the 8250_of driver. However it unconditionally uses the assert/deassert pair to deassert reset on the device at probe and assert it at remove. This does not work with systems that have a self-deasserting reset controller, such as Gemini, that recently added a reset controller. As a result, the console will not probe on the Gemini with this message: Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled of_serial: probe of 42000000.serial failed with error -524 This (-ENOTSUPP) is the error code returned by the deassert() operation on self-deasserting reset controllers. To work around this, implement dummy .assert() and .deassert() operations in the Gemini combined clock and reset controller. This fixes the issue on this system. Cc: Joel Stanley <joel@jms.id.au> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-serial@vger.kernel.org Fixes: e2860e1f62f2 ("serial: 8250_of: Add reset support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-07-15Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds
Pull MIPS updates from Ralf Baechle: "Boston platform support: - Document DT bindings - Add CLK driver for board clocks CM: - Avoid per-core locking with CM3 & higher - WARN on attempt to lock invalid VP, not BUG CPS: - Select CONFIG_SYS_SUPPORTS_SCHED_SMT for MIPSr6 - Prevent multi-core with dcache aliasing - Handle cores not powering down more gracefully - Handle spurious VP starts more gracefully DSP: - Add lwx & lhx missaligned access support eBPF: - Add MIPS support along with many supporting change to add the required infrastructure Generic arch code: - Misc sysmips MIPS_ATOMIC_SET fixes - Drop duplicate HAVE_SYSCALL_TRACEPOINTS - Negate error syscall return in trace - Correct forced syscall errors - Traced negative syscalls should return -ENOSYS - Allow samples/bpf/tracex5 to access syscall arguments for sane traces - Cleanup from old Kconfig options in defconfigs - Fix PREF instruction usage by memcpy for MIPS R6 - Fix various special cases in the FPU eulation - Fix some special cases in MIPS16e2 support - Fix MIPS I ISA /proc/cpuinfo reporting - Sort MIPS Kconfig alphabetically - Fix minimum alignment requirement of IRQ stack as required by ABI / GCC - Fix special cases in the module loader - Perform post-DMA cache flushes on systems with MAARs - Probe the I6500 CPU - Cleanup cmpxchg and add support for 1 and 2 byte operations - Use queued read/write locks (qrwlock) - Use queued spinlocks (qspinlock) - Add CPU shared FTLB feature detection - Handle tlbex-tlbp race condition - Allow storing pgd in C0_CONTEXT for MIPSr6 - Use current_cpu_type() in m4kc_tlbp_war() - Support Boston in the generic kernel Generic platform: - yamon-dt: Pull YAMON DT shim code out of SEAD-3 board - yamon-dt: Support > 256MB of RAM - yamon-dt: Use serial* rather than uart* aliases - Abstract FDT fixup application - Set RTC_ALWAYS_BCD to 0 - Add a MAINTAINERS entry core kernel: - qspinlock.c: include linux/prefetch.h Loongson 3: - Add support Perf: - Add I6500 support SEAD-3: - Remove GIC timer from DT - Set interrupt-parent per-device, not at root node - Fix GIC interrupt specifiers SMP: - Skip IPI setup if we only have a single CPU VDSO: - Make comment match reality - Improvements to time code in VDSO" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (86 commits) locking/qspinlock: Include linux/prefetch.h MIPS: Fix MIPS I ISA /proc/cpuinfo reporting MIPS: Fix minimum alignment requirement of IRQ stack MIPS: generic: Support MIPS Boston development boards MIPS: DTS: img: Don't attempt to build-in all .dtb files clk: boston: Add a driver for MIPS Boston board clocks dt-bindings: Document img,boston-clock binding MIPS: Traced negative syscalls should return -ENOSYS MIPS: Correct forced syscall errors MIPS: Negate error syscall return in trace MIPS: Drop duplicate HAVE_SYSCALL_TRACEPOINTS select MIPS16e2: Provide feature overrides for non-MIPS16 systems MIPS: MIPS16e2: Report ASE presence in /proc/cpuinfo MIPS: MIPS16e2: Subdecode extended LWSP/SWSP instructions MIPS: MIPS16e2: Identify ASE presence MIPS: VDSO: Fix a mismatch between comment and preprocessor constant MIPS: VDSO: Add implementation of gettimeofday() fallback MIPS: VDSO: Add implementation of clock_gettime() fallback MIPS: VDSO: Fix conversions in do_monotonic()/do_monotonic_coarse() MIPS: Use current_cpu_type() in m4kc_tlbp_war() ...
2017-07-11clk: boston: Add a driver for MIPS Boston board clocksPaul Burton
Add a driver for the clocks provided by the MIPS Boston board from Imagination Technologies. 2 clocks are provided - the system clock & the CPU clock - and each is a simple fixed rate clock whose frequency can be determined by reading a register provided by the board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-06-29clk: gemini: Read status before using the valueJoel Stanley
The probe does a shift and mask of val without having read it from the hardware. Fixes: 846423f96721 ("clk: Add Gemini SoC clock controller") Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-29clk: scpi: error when clock fails to registerJerome Brunet
Current implementation of scpi_clk_add just print a warning when clock fails to register but then keep going as if nothing happened. The provider is then registered with bogus data. This may latter lead to an Oops in __clk_create_clk when hlist_add_head(&clk->clks_node, &hw->core->clks) is called. This patch fixes the issue and errors if a clock fails to register. Fixes: cd52c2a4b5c4 ("clk: add support for clocks provided by SCP(System Control Processor)") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-29clk: at91: Add sama5d2 suspend/resumeAlexandre Belloni
On sama5d2, VDD core maybe be cut while in suspend. This means registers will be lost. Ensure they are saved and restored properly. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-22clk: keystone: TI_SCI_PROTOCOL is needed for clk driverArnd Bergmann
CONFIG_COMPILE_TEST allows building a configuration without TI_SCI_PROTOCOL, which then fails to link: drivers/clk/keystone/sci-clk.o: In function `ti_sci_clk_probe': sci-clk.c:(.text.ti_sci_clk_probe+0x4c): undefined reference to `devm_ti_sci_get_handle' This makes it a hard dependency. Right now, that means we can't actually compile-test the driver unless ARCH_KEYSTONE is set as well, but we can fix that by allowing TI_MESSAGE_MANAGER to be selected for COMPILE_TEST as well. Fixes: b745c0794e2f ("clk: keystone: Add sci-clk driver support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-22clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLLKrzysztof Kozlowski
Similarly to commit f1e9203e2366 ("clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated") for Exynos5420, the Exynos4412 also requires that EPLL is not disabled. Otherwise any access to MAUDIO block will silently halt. This was not visible before because EPLL on Exynos4 could not be disabled before commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX clocks"). After this commit, on Odroid U3 board one can see silent hang, usually with last (but unrelated) messages: [ 2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0 [ 2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci [ 2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653) Mark Exynos4 variant as also needed EPLL to be enabled all the time. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: uniphier: provide NAND controller clock rateMasahiro Yamada
This allows the NAND driver to get the clock rate via clk_get_rate(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: hisilicon: add usb2 clocks for hi3798cv200 SoCJiancheng Xue
Add usb2 clocks for hi3798cv200 SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: Add Gemini SoC clock controllerLinus Walleij
The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock controller that derive all clocks from a single crystal, using some documented and some undocumented PLLs, half dividers, counters and gates. This is a best attempt to construct a clock driver for the clocks so at least we can gate off unused hardware and driver the PCI bus clock. Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [sboyd@codeaurora.org: Fix devm_ioremap_resource() return value checking] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-21clk: iproc: Remove __init marking on iproc_pll_clk_setup()Stephen Boyd
Now that this function is called from driver probe routines, it needs to drop the __init marking because it isn't just called from init code. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Cc: Anup Patel <anup.patel@broadcom.com> Cc: Ray Jui <ray.jui@broadcom.com> Cc: Scott Branden <scott.branden@broadcom.com> Fixes: 654cdd3229cd ("clk: bcm: Add clocks for Stingray SOC") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: bcm: Add clocks for Stingray SOCSandeep Tripathy
This patch adds support for Stingray clocks in iproc ccf. The Stingray SOC has various plls based on iproc pll architecture. Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang
The patch enables CPU multiplexer clock on MT8173 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: export cpu multiplexer clock for MT2701/MT7623 SoCsSean Wang
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes up cpufreq driver fails at acquiring intermediate clock source when driver probe is called. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't workSean Wang
This patch adds CPU multiplexer clocks which are essential for Mediatek cpufreq driver. It would use the CPU clock multiplexer to switch to the intermediate clock source temporarily and then wait for the primary clock changing getting stable. Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: renesas: cpg-mssr: Use of_device_get_match_data() helperGeert Uytterhoeven
If CONFIG_OF=n: drivers/clk/renesas/renesas-cpg-mssr.c: In function ‘cpg_mssr_probe’: drivers/clk/renesas/renesas-cpg-mssr.c:702: warning: dereferencing ‘void *’ pointer drivers/clk/renesas/renesas-cpg-mssr.c:702: error: request for member ‘data’ in something not a structure or union To fix this, use the of_device_get_match_data() helper, for which a dummy version is provided if CONFIG_OF=n. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi6220: add acpu clockZhangfei Gao
Add acpu clock, including sft clock controlling hi6220 coresight module Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: zx296718: export I2S mux clocksShawn Guo
Export I2S mux clocks, so that device tree can refer to them for setting a better parent clock for I2S work clock. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: imx7d: create clocks behind rawnand clock gateStefan Agner
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi3660: Set PPLL2 to 2880MZhong Kaihua
Set PPLL2 to 2880M. With this patch, we saw better compatibility on various 1080p HDMI monitors. Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Zheng Shaobo <zhengshaobo1@huawei.com> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> [sboyd@codeaurora.org: Add UL to long number to silence C90 warning] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi3660: add clocks for video encoder, decoder and ISPChen Jun
This patch adds more clocks for hi3660, including: - video encoder and decoder - ISP (Image Signal Processing) Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: hi3660: fix wrong parent name of clk_mux_sysbusChen Jun
Parent name of clk_mux_sysbus is not correct. This patch fixes it. Signed-off-by: Chen Jun <chenjun14@huawei.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Guodong Xu <guodong.xu@linaro.org> Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: gcc-msm8916: add support to 9.6MHz codec clkSrinivas Kandagatla
MCLK for internal audio codec is expected to be at 9.6MHz by default. This patch adds support to 9.6MHz to make the default case possible. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: qcom: Add ipq8074 Global Clock Controller supportAbhishek Sahu
This patch adds support for the global clock controller found on the ipq8074 based devices. This includes UART, I2C, SPI etc. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mvebu: cp110: Minor cleanupsStephen Boyd
Mark an array of strings static const and remove the dereference of a function pointer when assigning to the platform driver probe struct member. drivers/clk/mvebu/cp110-system-controller.c:89:12: warning: symbol 'gate_base_names' was not declared. Should it be static? drivers/clk/mvebu/cp110-system-controller.c:447:18: error: cannot dereference this type Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19Merge branch 'clk-cp110' of git://git.infradead.org/linux-mvebu into clk-nextStephen Boyd
Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT: We got more information about the clock controllers and the clock tree of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The clk driver is modified accordingly from this new information. * 'clk-cp110' of git://git.infradead.org/linux-mvebu: clk: mvebu: cp110: add sdio clock to cp-110 system controller clk: mvebu: cp110: introduce a new binding clk: mvebu: cp110: do not depend anymore of the *-clock-output-names clk: mvebu: cp110: make failure labels more meaningful
2017-06-19clk: socfpga: Fix the smplsel on Arria10 and Stratix10Dinh Nguyen
The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are offset by 1 additional bit. Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and Stratix10 platforms. Fixes: 5611a5ba8e54 ("clk: socfpga: update clk.h so for Arria10 platform to use") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVERLeo Yan
The timer will register into system at very early phase at kernel boot; if timer needs to use clock, the clock should be get ready in function of_clk_init() so later the timer driver probe can retrieve clock successfully. This is finished in below flow on arm64: start_kernel() `-> time_init() `-> of_clk_init(NULL) => register timer's clock `-> clocksource_probe() => register timer On Hi3660 the sp804 timer uses clock "osc32k", this clock is registered as platform driver rather than CLK_OF_DECLARE_DRIVER method. As result, sp804 timer probe returns failure due if cannot bind clock properly. To fix the failure, this patch is to split crgctrl clocks into two subsets. One part is for fixed_rate_clks which includes pre-defined fixed rate clocks, and "osc32k" clock is in this category; So we change their registration to CLK_OF_DECLARE_DRIVER method, as result the clocks can be registered ahead with function of_clk_init() and timer driver can bind timer clock successfully; the rest of the crgctrl clocks are still registered by the probe of the platform driver. This patch also adds checking for all crgctrl clocks registration and print out log if any clock has failure. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-19clk: mvebu: cp110: add sdio clock to cp-110 system controllerKonstantin Porotchkin
This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-19clk: mvebu: cp110: introduce a new bindingGregory CLEMENT
The initial intent when the binding of the cp110 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-19clk: mvebu: cp110: do not depend anymore of the *-clock-output-namesGregory CLEMENT
Using the *-clock-output-names property was a convenient way to have a unique name for each clock even when there are multiple cp110 blocks as we can find on Armada 8K. However it has some drawbacks: the main one being a stronger link than necessary between the driver and the device tree. For example the clock name can't be changed, removed or moved. It is still the early stage of introduction of the Armada 7K/8K and the hardware is still not totally documented, especially for the clock part. By removing the use of *-clock-output-names it will be easier to add new clocks without breaking the compatibility. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2017-06-16Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd
clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
2017-06-16Merge branch 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm ↵Stephen Boyd
into clk-next * 'for-4.13-ti-clkctrl' of https://github.com/t-kristo/linux-pm: clk: ti: omap4: add clkctrl clock data dt-bindings: clk: add omap4 clkctrl definitions clk: ti: add support for clkctrl clocks Documentation: dt-bindings: Add binding documentation for TI clkctrl clocks
2017-06-16clk: sunxi-ng: Staticize ccu_mux_helper_unapply_prediv()Stephen Boyd
It isn't used outside of this file right now. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-06-16Merge tag 'sunxi-clk-for-4.13' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull Allwinner clock patches from Maxime Ripard: Some new clock units are supported, for the display clocks unsed in the newer SoCs, and the A83T PRCM. There is also a bunch of minor fixes for clocks that are not used by anyone, and reworks needed by drivers that will land in 4.13. * tag 'sunxi-clk-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (21 commits) clk: sunxi-ng: Move all clock types to a library clk: sunxi-ng: a83t: Add support for A83T's PRCM dt-bindings: clock: sunxi-ccu: Add compatible string for A83T PRCM clk: sunxi-ng: select SUNXI_CCU_MULT for sun8i-a83t clk: sunxi-ng: a83t: Fix audio PLL divider offset clk: sunxi-ng: a83t: Fix PLL lock status register offset clk: sunxi-ng: Add driver for A83T CCU clk: sunxi-ng: Support multiple variable pre-dividers dt-bindings: clock: sunxi-ccu: Add compatible string for A83T CCU clk: sunxi-ng: de2: fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: sun5i: Export video PLLs clk: sunxi-ng: mux: Re-adjust parent rate clk: sunxi-ng: mux: Change pre-divider application function prototype clk: sunxi-ng: mux: split out the pre-divider computation code clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT clk: sunxi-ng: div: Switch to divider_round_rate clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate clk: divider: Make divider_round_rate take the parent clock clk: sunxi-ng: explicitly include linux/spinlock.h clk: sunxi-ng: add support for DE2 CCU ...
2017-06-16clk: meson: gxbb: add all clk81 parentsJerome Brunet
Remove the FIXME on clk81 mux and add all the documented parents Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-06-16Merge branch 'next/headers' into next/driversJerome Brunet
2017-06-15clk: ti: omap4: add clkctrl clock dataTero Kristo
Add data for omap4 clkctrl clocks, and register it within the clkctrl driver. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-06-15clk: ti: add support for clkctrl clocksTero Kristo
Previously, hwmod core has been used for controlling the hwmod level clocks directly. This has certain drawbacks, like being unable to share the clocks for multiple users, missing usecounting and generally being totally incompatible with the common clock framework. This patch adds support for clkctrl clocks for addressing the above issues. These support the modulemode handling, which will replace the direct hwmod clkctrl linkage. Any optional clocks are also supported, gate, mux and divider. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2017-06-14Merge branch 'clk-fixes' into clk-nextStephen Boyd
* clk-fixes: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
2017-06-14Merge tag 'sunxi-clk-fixes-for-4.12' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes Allwinner clock fixes for 4.12 Some fixes that fix some bindings that went in 4.12, fix a few reset and clock offsets and a build error fix * tag 'sunxi-clk-fixes-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
2017-06-14Merge tag 'clk-v4.13-samsung' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next Pull samsung clk driver updates from Sylwester Nawrocki - conversion to the clk_hw API - definitions and fixes of exynos5420 SoC audio subsystem related clocks * tag 'clk-v4.13-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: exynos542x: Add EPLL rate table clk: samsung: Add missing exynos5420 audio related clocks clk: samsung: Add enable/disable operation for PLL36XX clocks clk: samsung: s5pv210-audss: Convert to the new clk_hw API clk: samsung: exynos-clkout: Convert to the new clk_hw API clk: samsung: exynos-audss: Convert to the new clk_hw API clk: samsung: Convert common drivers to the new clk_hw API clk: samsung: Add local variable to match its purpose clk: samsung: Remove dead code
2017-06-14Merge tag 'v4.13-rockchip-clk1' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: One new clock controller for the rk3128 soc, a fixup for the rk3228 cpuclk table and the usual bunch of some new clock-ids and some clocks marked as critical. * tag 'v4.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: mark some special clk as critical on rk3368 clk: rockchip: mark noc and some special clk as critical on rk3288 clk: rockchip: mark noc and some special clk as critical on rk3228 clk: rockchip: mark pclk_ddrupctl as critical_clock on rk3036 clk: rockchip: add clock controller for rk3128 dt-bindings: add bindings for rk3128 clock controller clk: rockchip: export more rk3228 clocks ids clk: rockchip: add ids for rk3399 testclks used for camera handling clk: rockchip: add dt-binding header for rk3128 clk: rockchip: fix up the RK3228 clk cpu setting table clk: rockchip: add clock-ids for more rk3228 clocks clk: rockchip: add ids for camera on rk3399
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 01:57:07 +0000