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path: root/drivers/clk
AgeCommit message (Expand)Author
2018-01-02clk: qcom: Add APCS clock controller supportGeorgi Djakov
2018-01-02clk: qcom: Add regmap mux-div clocks supportGeorgi Djakov
2018-01-02clk: qcom: Add A53 PLL supportGeorgi Djakov
2017-12-29clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCUIcenowy Zheng
2017-12-29clk: sunxi-ng: add support for Allwinner H3 DE2 CCUIcenowy Zheng
2017-12-28clk: divider: fix incorrect usage of container_ofJerome Brunet
2017-12-28clk: mvebu: armada-37xx-periph: Use PTR_ERR_OR_ZERO()Gomonovych, Vasyl
2017-12-28clk: iproc: Minor tidy up of iproc pll data structuresLori Hikichi
2017-12-28clk: iproc: Allow plls to do minor rate changes without resetLori Hikichi
2017-12-28clk: iproc: Fix error in the pll post divider rate calculationLori Hikichi
2017-12-28clk: iproc: Allow iproc pll to runtime calculate vco parametersLori Hikichi
2017-12-28clk: si5351: _si5351_clkout_reset_pll() can be staticWu Fengguang
2017-12-28clk: pxa: unbreak lookup of CLK_POUTIgor Grinberg
2017-12-28clk: meson-axg: make local symbol axg_gp0_params_table staticweiyongjun (A)
2017-12-28clk: meson-axg: fix return value check in axg_clkc_probe()weiyongjun (A)
2017-12-26clk: use atomic runtime pm api in clk_core_is_enabledDong Aisheng
2017-12-26clk: mediatek: Fix all warnings for missing struct clk_onecell_dataSean Wang
2017-12-23clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl
2017-12-21clk: si5351: Do not enable parent clocks on probeSergej Sawazki
2017-12-21clk: si5351: Rename internal plls to avoid name collisionsSergej Sawazki
2017-12-21clk: si5351: Apply PLL soft reset before enabling the outputsSergej Sawazki
2017-12-21clk: si5351: Add DT property to enable PLL resetSergej Sawazki
2017-12-21clk: si5351: implement remove handlerAlexey Khoroshilov
2017-12-21clk: axi-clkgen: Round closest in round_rate() and recalc_rate()Lars-Peter Clausen
2017-12-21clk: axi-clkgen: Correctly handle nocount bit in recalc_rate()Lars-Peter Clausen
2017-12-21clk: Don't touch hardware when reparenting during registrationStephen Boyd
2017-12-21clk: mediatek: fixup test-building of MediaTek clock driversSean Wang
2017-12-21clk: mediatek: group drivers under indpendent menuSean Wang
2017-12-21clk: at91: pmc: Support backup for programmable clocksRomain Izard
2017-12-21clk: at91: pmc: Save SCSR during suspendRomain Izard
2017-12-21clk: at91: pmc: Wait for clocks when resumingRomain Izard
2017-12-21clk: qcom: ipq8074: add misc resets for PCIE and NSSAbhishek Sahu
2017-12-21clk: qcom: ipq8074: add GP and Crypto clocksAbhishek Sahu
2017-12-21clk: qcom: ipq8074: add NSS ethernet port clocksAbhishek Sahu
2017-12-21clk: qcom: ipq8074: add NSS clocksAbhishek Sahu
2017-12-21clk: qcom: ipq8074: add PCIE, USB and SDCC clocksAbhishek Sahu
2017-12-21clk: qcom: ipq8074: add remaining PLL’sAbhishek Sahu
2017-12-21clk: qcom: ipq8074: fix missing GPLL0 divider widthAbhishek Sahu
2017-12-21clk: qcom: add parent map for regmap muxAbhishek Sahu
2017-12-21clk: qcom: add read-only divider operationsAbhishek Sahu
2017-12-21clk: imx51: uart4, uart5 gates only exist on imx50, imx53Philipp Zabel
2017-12-21clk: qoriq: add more divider clocks supportYuantian Tang
2017-12-21clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocksGregory CLEMENT
2017-12-21clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFSGregory CLEMENT
2017-12-21clk: mvebu: armada-37xx-periph: cosmetic changesGregory CLEMENT
2017-12-21clk: sprd: add clocks support for SC9860Chunyan Zhang
2017-12-21clk: sprd: add adjustable pll supportChunyan Zhang
2017-12-21clk: sprd: add composite clock supportChunyan Zhang
2017-12-21clk: sprd: add divider clock supportChunyan Zhang
2017-12-21clk: sprd: add mux clock supportChunyan Zhang