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path: root/drivers/clk/sunxi-ng/ccu_div.c
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2017-12-28clk: divider: fix incorrect usage of container_ofJerome Brunet
divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-14clk: sunxi-ng: div: Add support for fixed post-dividerPriit Laes
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where 6 is fixed post-divider. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: mux: Change pre-divider application function prototypeMaxime Ripard
The current function name is a bit confusing, and doesn't really allow to create an explicit function to reverse the operation. We also for now change the parent rate through a pointer, while we don't return anything. In order to be less confusing, and easier to use for downstream users, change the function name to something hopefully clearer, and return the adjusted rate instead of changing the pointer. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: div: Switch to divider_round_rateMaxime Ripard
divider_round_rate_parent already evaluates changing the parent rate if CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's just use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-06-07clk: sunxi-ng: Pass the parent and a pointer to the clocks round rateMaxime Ripard
The clocks might need to modify their parent clocks. In order to make that possible, give them access to the parent clock being evaluated, and to a pointer to the parent rate so that they can modify it if needed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2017-01-27clk: sunxi-ng: Call divider_round_rate if we only have a single parentMaxime Ripard
The divider_get_val function that is used in our determine_rate callback doesn't try to change the parent rate at all, while clk_divider_bestdiv, used in divider_round_rate, does. If we have a single parent, call divider_round_rate. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
2016-07-08clk: sunxi-ng: Add dividerMaxime Ripard
Add support for the various dividers (linear, table or pow-of-two based) found in the CCU. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-8-maxime.ripard@free-electrons.com