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path: root/drivers/clk/meson
AgeCommit message (Expand)Author
2020-10-28clk: define to_clk_regmap() as inline functionArnd Bergmann
2020-10-20Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ...Stephen Boyd
2020-10-13clk: meson: use semicolons rather than commas to separate statementsJulia Lawall
2020-09-10clk: meson: make shipped controller configurableJerome Brunet
2020-08-29clk: meson: g12a: mark fclk_div2 as criticalStefan Agner
2020-08-17clk: meson: axg-audio: fix g12a tdmout sclk inverterJerome Brunet
2020-08-17clk: meson: axg-audio: separate axg and g12a regmap tablesJerome Brunet
2020-08-17clk: meson: add sclk-ws driverJerome Brunet
2020-07-21Merge branch 'clk-amlogic' into clk-nextStephen Boyd
2020-07-10Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov
2020-07-09clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl
2020-07-09clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl
2020-06-24clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl
2020-06-19clk: meson: g12a: Add support for NNA CLK source clocksDmitry Shmidt
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl
2020-04-16clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl
2020-04-16clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl
2020-04-14clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl
2020-04-14clk: meson8b: export the HDMI system clockMartin Blumenstingl
2020-02-21clk: meson: meson8b: set audio output clock hierarchyMartin Blumenstingl
2020-02-19clk: meson: g12a: add support for the SPICC SCLK Source clocksNeil Armstrong
2020-02-13clk: meson: gxbb: set audio output clock hierarchyJerome Brunet
2020-02-13clk: meson: gxbb: add the gxl internal dac gateJerome Brunet
2020-01-31Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlo...Stephen Boyd
2020-01-07clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl
2019-12-23clk: let init callback return an error codeJerome Brunet
2019-12-16Merge branch 'v5.5/fixes' into v5.6/driversJerome Brunet
2019-12-16clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel
2019-12-16clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet
2019-12-11clk: meson: meson8b: use of_clk_hw_register to register the clocksMartin Blumenstingl
2019-12-11clk: meson: meson8b: don't register the XTAL clock when provided via OFMartin Blumenstingl
2019-12-11clk: meson: meson8b: change references to the XTAL clock to use [fw_]nameMartin Blumenstingl
2019-12-11clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifierMartin Blumenstingl
2019-12-11clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controllerMartin Blumenstingl
2019-10-14clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify codeYueHaibing
2019-10-08clk: meson: axg_audio: add sm1 supportJerome Brunet
2019-10-08clk: meson: axg-audio: provide clk top signal nameJerome Brunet
2019-10-08clk: meson: axg-audio: prepare sm1 additionJerome Brunet
2019-10-08clk: meson: axg-audio: fix regmap last registerJerome Brunet
2019-10-08clk: meson: axg-audio: remove useless definesJerome Brunet
2019-10-01clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxesNeil Armstrong
2019-10-01clk: meson: g12a: fix cpu clock rate settingNeil Armstrong
2019-10-01clk: meson: gxbb: let sar_adc_clk_div set the parent clock rateMartin Blumenstingl
2019-09-19Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' i...Stephen Boyd
2019-08-26clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocksNeil Armstrong
2019-08-26clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clockNeil Armstrong