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path: root/drivers/clk/meson
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2021-06-30clk: meson: regmap: switch to determine_rate for the dividersMartin Blumenstingl
This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210627223959.188139-4-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-09clk: meson: g12a: Add missing NNA source clocks for g12bNick Xie
This adds the Neural Network Accelerator source clocks for g12b. Initial support for sm1 already exist in commit 2f1efa5340ef ("clk: meson: g12a: Add support for NNA CLK source clocks") The sm1 and g12b share the same NNA source clocks. This patch add missing NNA clocks for A311D (g12b). Signed-off-by: Nick Xie <nick@khadas.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210604032957.224496-1-xieqinick@gmail.com
2021-05-24clk: meson: axg-audio: improve deferral handlingJerome Brunet
Use dev_err_probe() for clock and reset resources to indicate the deferral reason through sysfs when waiting for the resource to come up. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210520073136.272925-1-jbrunet@baylibre.com
2021-05-20clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet
While some SoC samples are able to lock with a PLL factor of 55, others samples can't. ATM, a minimum of 60 appears to work on all the samples I have tried. Even with 60, it sometimes takes a long time for the PLL to eventually lock. The documentation says that the minimum rate of these PLLs DCO should be 3GHz, a factor of 125. Let's use that to be on the safe side. With factor range changed, the PLL seems to lock quickly (enough) so far. It is still unclear if the range was the only reason for the delay. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210429090325.60970-1-jbrunet@baylibre.com
2021-05-19clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl
This increases the maxmium supported frequency on 32-bit systems from 2^31 (signed long as used by clk_ops.round_rate, maximum value: approx. 2.14GHz) to 2^32 (unsigned long as used by clk_ops.determine_rate, maximum value: approx. 4.29GHz). On Meson8/8b/8m2 the HDMI PLL and it's OD (post-dividers) are capable of running at up to 2.97GHz. So switch the divider implementation in clk-regmap to clk_ops.determine_rate to support these higher frequencies on 32-bit systems. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20210517203724.1006254-4-martin.blumenstingl@googlemail.com
2021-02-09clk: meson: axg: Remove MIPI enable clock gateRemi Pommarel
On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY region and is not related to clock one and can be removed from it. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2021-01-04clk: meson: meson8b: remove compatibility code for old .dtbsMartin Blumenstingl
The XTAL clock is provided via .dts since Linux 5.6. Remove compatibility code for .dtbs which are older than that. The switch to the HHI syscon has been done with Linux 5.1. Also remove any code needed to support .dtbs that have not switched to the HHI syscon yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201221183624.932649-2-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl
Popagate the error code from meson_clk_pll_set_rate() when the PLL does not lock with the new settings. Fixes: 722825dcd54b2e ("clk: meson: migrate plls clocks to clk_regmap") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-4-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl
The error codes returned by meson_clk_get_pll_settings() are all negative. Make "ret" a signed integer in meson_clk_pll_set_rate() to make it match with the clk_ops.set_rate API as well as the data type returned by meson_clk_get_pll_settings(). Fixes: 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-3-martin.blumenstingl@googlemail.com
2021-01-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl
The "rate" parameter in meson_clk_pll_set_rate() contains the new rate. Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try to switch from the new rate to the same rate again. Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201226121556.975418-2-martin.blumenstingl@googlemail.com
2020-12-21Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework got some nice improvements this time around. We gained the ability to get struct clk pointers from a struct clk_hw so that clk providers can consume the clks they provide, if they need to do something like that. This has been a long missing part of the clk provider API that will help us move away from exposing a struct clk pointer in the struct clk_hw. Tracepoints are added for the clk_set_rate() "range" functions, similar to the tracepoints we already have for clk_set_rate() and we added a column to debugfs to help developers understand the hardware enable state of clks in case firmware or bootloader state is different than what is expected. Overall the core changes are mostly improving the clk driver writing experience. At the driver level, we have the usual collection of driver updates and new drivers for new SoCs. This time around the Qualcomm folks introduced a good handful of clk drivers for various parts of three or four SoCs. The SiFive folks added a new clk driver for their FU740 SoCs, coming in second on the diffstat and then Atmel AT91 and Amlogic SoCs had lots of work done after that for various new features. One last thing to note in the driver area is that the i.MX driver has gained a new binding to support SCU clks after being on the list for many months. It uses a two cell binding which is sort of rare in clk DT bindings. Beyond that we have the usual set of driver fixes and tweaks that come from more testing and finding out that some configuration was wrong or that a driver could support being built as a module. Summary: Core: - Add some trace points for clk_set_rate() "range" functions - Add hardware enable information to clk_summary debugfs - Replace clk-provider.h with of_clk.h when possible - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw New Drivers: - Bindings for Canaan K210 SoC clks - Support for SiFive FU740 PRCI - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs Updates: - DVFS support for AT91 clk driver - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on Renesas R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on Renesas RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors in Renesas clk drivers - One more conversion of DT bindings to json-schema - Make i.MX clk-gate2 driver more flexible - New two cell binding for i.MX SCU clks - Drop of_match_ptr() in i.MX8 clk drivers - Add arch dependencies for Rockchip clk drivers - Fix i2s on Rockchip rk3066 - Add MIPI DSI clks on Amlogic axg and g12 SoCs - Support modular builds of Amlogic clk drivers - Fix an Amlogic Video PLL clock dependency - Samsung Kconfig dependencies updates for better compile test coverage - Refactoring of the Samsung PLL clocks driver - Small Tegra driver cleanups - Minor fixes to Ingenic and VC5 clk drivers - Cleanup patches to remove unused variables and plug memory leaks" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (134 commits) dt-binding: clock: Document canaan,k210-clk bindings dt-bindings: Add Canaan vendor prefix clk: vc5: Use "idt,voltage-microvolt" instead of "idt,voltage-microvolts" clk: ingenic: Fix divider calculation with div tables clk: sunxi-ng: Make sure divider tables have sentinel clk: s2mps11: Fix a resource leak in error handling paths in the probe function clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 clk: si5351: Wait for bit clear after PLL reset clk: at91: sam9x60: remove atmel,osc-bypass support clk: at91: sama7g5: register cpu clock clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: fix compilation error ...
2020-11-26clk: meson: g12a: add MIPI DSI Host Pixel ClockNeil Armstrong
This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201126141600.2084586-3-narmstrong@baylibre.com
2020-11-23clk: meson: enable building as modulesKevin Hilman
Make it possible to build all clk drivers as modules, but default remains built-in. No functional changes. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201118191405.36798-1-khilman@baylibre.com
2020-11-23clk: meson: Kconfig: fix dependency for G12AKevin Hilman
When building only G12A, ensure that VID_PLL_DIV clock driver is selected, otherwise results in this build error: ERROR: modpost: "meson_vid_pll_div_ro_ops" [drivers/clk/meson/g12a.ko] undefined! Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201118190930.34352-1-khilman@baylibre.com
2020-11-23clk: meson: axg: add MIPI DSI Host clockNeil Armstrong
This adds the MIPI DSI Host clock, used to measure the signal timings (ENC VSYNC or DW-MIPI-DSI eDPI timings). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200915124553.8056-5-narmstrong@baylibre.com
2020-11-23clk: meson: axg: add Video ClocksNeil Armstrong
Add the clocks entries used in the video clock path, the clock path is doubled to permit having different synchronized clocks for different parts of the video pipeline. The AXG only has a single ENCL CTS clock and even if VCLK exist along VCLK2, only VCLK2 is used since it clocks the MIPI DSI IP directly. All dividers are flagged with CLK_GET_RATE_NOCACHE, and all gates are flagged with CLK_IGNORE_UNUSED since they are currently directly handled by the Meson DRM Driver. Once the DRM Driver is fully migrated to using the Common Clock Framework to handle the video clock tree, the CLK_GET_RATE_NOCACHE and CLK_IGNORE_UNUSED will be dropped. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200915124553.8056-4-narmstrong@baylibre.com
2020-11-14clk: meson: g12: use devm variant to register notifiersJerome Brunet
Until now, nothing was done to unregister the dvfs clock notifiers of the Amlogic g12 SoC family. This is not great but this driver was not really expected to be unloaded. With the ongoing effort to build everything as module for this platform, this needs to be cleanly handled. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201021163847.595189-3-jbrunet@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-11-14clk: meson: g12: drop use of __clk_lookup()Jerome Brunet
g12 clock controller used __clk_lookup() to get struct clk from a struct clk_hw. This type of hack is no longer required as CCF now provides the necessary functions to get this. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201021162147.563655-4-jbrunet@baylibre.com Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-28clk: define to_clk_regmap() as inline functionArnd Bergmann
Nesting container_of() causes warnings with W=2, which is annoying if it happens in headers and fills the build log like: In file included from drivers/clk/qcom/clk-alpha-pll.c:6: drivers/clk/qcom/clk-alpha-pll.c: In function 'clk_alpha_pll_hwfsm_enable': include/linux/kernel.h:852:8: warning: declaration of '__mptr' shadows a previous local [-Wshadow] 852 | void *__mptr = (void *)(ptr); \ | ^~~~~~ drivers/clk/qcom/clk-alpha-pll.c:155:31: note: in expansion of macro 'container_of' 155 | #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ | ^~~~~~~~~~~~ drivers/clk/qcom/clk-regmap.h:27:28: note: in expansion of macro 'container_of' 27 | #define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw) | ^~~~~~~~~~~~ drivers/clk/qcom/clk-alpha-pll.c:155:44: note: in expansion of macro 'to_clk_regmap' 155 | #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \ | ^~~~~~~~~~~~~ drivers/clk/qcom/clk-alpha-pll.c:254:30: note: in expansion of macro 'to_clk_alpha_pll' 254 | struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); | ^~~~~~~~~~~~~~~~ include/linux/kernel.h:852:8: note: shadowed declaration is here 852 | void *__mptr = (void *)(ptr); \ | ^~~~~~ Redefine two copies of the to_clk_regmap() macro as inline functions to avoid a lot of these. Fixes: ea11dda9e091 ("clk: meson: add regmap clocks") Fixes: 085d7a455444 ("clk: qcom: Add a regmap type clock struct") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20201026161411.3708639-1-arnd@kernel.org Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-20Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ↵Stephen Boyd
'clk-const' and 'clk-mmp2' into clk-next * clk-semicolon: clk: meson: use semicolons rather than commas to separate statements clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements clk: uniphier: use semicolons rather than commas to separate statements * clk-axi-clkgen: clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers * clk-qoriq: clk: qoriq: modify MAX_PLL_DIV to 32 * clk-baikal: clk: baikal-t1: Mark Ethernet PLL as critical * clk-const: clk: pxa: Constify static struct clk_ops * clk-mmp2: clk: mmp2: Fix the display clock divider base
2020-10-13clk: meson: use semicolons rather than commas to separate statementsJulia Lawall
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1601233948-11629-11-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-10clk: meson: make shipped controller configurableJerome Brunet
Add the necessary bits so unnecessary amlogic clock controllers can be compiled out. This allows to save a few kB when necessary. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200828154735.435374-1-jbrunet@baylibre.com
2020-08-29clk: meson: g12a: mark fclk_div2 as criticalStefan Agner
On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2 seems to be necessary for the system to operate correctly as well. Typically, the clock also gets chosen by the eMMC peripheral. This probably masked the problem so far. However, when booting from a SD card the clock seems to get disabled which leads to a system freeze. Let's mark this clock as critical, fixing boot from SD card on G12b platforms. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch
2020-08-17clk: meson: axg-audio: fix g12a tdmout sclk inverterJerome Brunet
Fix the tdmout inverter of the g12a and following SoC families. This inverter is special and needs two bits to be the inverse of each other for the inverter to operate properly. Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-4-jbrunet@baylibre.com
2020-08-17clk: meson: axg-audio: separate axg and g12a regmap tablesJerome Brunet
There are more differences than what we initially thought. Let's keeps things clear and separate the axg and g12a regmap tables of the audio clock controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-3-jbrunet@baylibre.com
2020-08-17clk: meson: add sclk-ws driverJerome Brunet
This is yet another simple but odd driver for the audio block of the g12a and sm1 SoC families. For TDMOUT's sclk to be properly inverted, bit 29 of AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28. IOW bit28 == !bit29 at all times This setting is automatically applied on axg and the manual setting was added on g12a. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com
2020-07-21Merge branch 'clk-amlogic' into clk-nextStephen Boyd
* clk-amlogic: clk: meson: meson8b: add the vclk2_en gate clock clk: meson: meson8b: add the vclk_en gate clock clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2 clk: meson: g12a: Add support for NNA CLK source clocks dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2020-07-10Replace HTTP links with HTTPS ones: Common CLK frameworkAlexander A. Klimov
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Link: https://lore.kernel.org/r/20200703175114.15027-1-grandmaster@al2klimov.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-09clk: meson: meson8b: add the vclk2_en gate clockMartin Blumenstingl
HHI_VIID_CLK_CNTL[19] is not part of the public S805 datasheet. However, the GXBB driver defines this bit as a gate called "vclk2" and in the 3.10 kernel GPL code dump the following line can found: WRITE_LCD_CBUS_REG_BITS(HHI_VIID_CLK_CNTL, 0, 19, 1); //disable vclk2_en Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller to complete the VCLK2 clock tree. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200629203904.2989007-3-martin.blumenstingl@googlemail.com
2020-07-09clk: meson: meson8b: add the vclk_en gate clockMartin Blumenstingl
HHI_VID_CLK_CNTL[19] is documented as CLK_EN0. This description is the same in the public S912 datasheet and the GXBB driver calls this gate "vclk". Add this gate clock to the Meson8/Meson8b/Meson8m2 clock controller because it's needed to make the video output work. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200629203904.2989007-2-martin.blumenstingl@googlemail.com
2020-06-24clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2Martin Blumenstingl
Drop CLK_IS_CRITICAL from fclk_div2. This was added because we didn't know the relation between this clock and RGMII Ethernet. It turns out that fclk_div2 is used as "timing adjustment clock" to generate the RX delay on the MAC side - which was enabled by u-boot on Odriod-C1. When using the RX delay on the PHY side or not using a RX delay at all then this clock can be disabled. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200620161422.24114-1-martin.blumenstingl@googlemail.com
2020-06-19clk: meson: g12a: Add support for NNA CLK source clocksDmitry Shmidt
This adds the Neural Network Accelerator source clocks hierarchy, it's 2 simple composite clocks to feed the AXI interface and the Core of the Neural Network Accelerator IP. This IP is only present on the Amlogic SM1 SoCs family. Signed-off-by: Dmitry Shmidt <dimitrysh@google.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200610083012.5024-3-narmstrong@baylibre.com
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl
Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers. In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when booting Linux the PLL fails to lock. The initialization sequence from u-boot is: - put the PLL into reset - write 0x59C88000 to HHI_GP_PLL_CNTL2 - write 0xCA463823 to HHI_GP_PLL_CNTL3 - write 0x0286A027 to HHI_GP_PLL_CNTL4 - write 0x00003000 to HHI_GP_PLL_CNTL5 - set M, N, OD and the enable bit - take the PLL out of reset - check if it has locked - disable the PLL In Linux we already initialize M, N, OD, the enable and the reset bits. Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the exact meaning is unknown) so the PLL can lock when the vendor u-boot did not initialize these registers yet. Fixes: b882964b376f21 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl
The "vpu_0" or "vpu_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1" tree when "vpu_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the VPU clock. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-5-martin.blumenstingl@googlemail.com
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl
The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL register: - HHI_VID_CLK_CNTL[0] = DIV1_EN - HHI_VID_CLK_CNTL[1] = DIV2_EN - HHI_VID_CLK_CNTL[2] = DIV4_EN - HHI_VID_CLK_CNTL[3] = DIV6_EN - HHI_VID_CLK_CNTL[4] = DIV12_EN Update the bits accordingly so we will enable the bits in the correct register once we switch these clocks to be mutable. Fixes: 6cb57c678bb70e ("clk: meson: meson8b: add the read-only video clock trees") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-4-martin.blumenstingl@googlemail.com
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means: - asserting them requires setting the register value to 0 - de-asserting them requires setting the register value to 1 Set the register value accordingly for these two reset lines by setting the inverted the register value compared to all other reset lines. Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl
Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not easy to see that the vendor kernel does the same, but it actually does. meson_clk_pll_ops in mainline still cannot fully recalculate all rates from the HDMI PLL registers because some register bits (at the time of writing it's unknown which bits are used for this) double the HDMI PLL output rate (compared to simply considering M, N and FRAC) for some (but not all) PLL settings. Update the vid_pll_in_sel parent so our clock calculation works for simple clock settings like the CVBS output (where no rate doubling is going on). The PLL ops need to be fixed later on for more complex clock settings (all HDMI rates). Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com
2020-04-16clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also propagate set_rate requests from the gate to the divider and from the divider to the the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Don't propagate rate changes to the mux parents because we don't want to change the MPLL clocks (these are reserved for audio). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200414195031.224021-3-martin.blumenstingl@googlemail.com
2020-04-16clk: meson: gxbb: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. Also propagate set_rate requests from the gate to the divider and from the divider to the the mux so the GPU clock frequency can be updated at runtime (which will be required for GPU DVFS). Don't propagate rate changes to the mux parents because we don't want to change the MPLL clocks (these are reserved for audio). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200414195031.224021-2-martin.blumenstingl@googlemail.com
2020-04-14clk: meson: meson8b: make the hdmi_sys clock tree mutableMartin Blumenstingl
The HDMI TX controller requires the hdmi_sys clock to be enabled. Allow changing the whole clock tree now that we know that one of our drivers requires this. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200330234535.3327513-3-martin.blumenstingl@googlemail.com
2020-04-14clk: meson8b: export the HDMI system clockMartin Blumenstingl
Export the HDMI system clock (used by the HDMI transmitter) so it can be used in the dt-bindings. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200330234535.3327513-2-martin.blumenstingl@googlemail.com
2020-02-21clk: meson: meson8b: set audio output clock hierarchyMartin Blumenstingl
The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to operate. Reflect this hierarchy in the clock tree. Fixes: e31a1900c1ff73 ("meson: clk: Add support for clock gates") Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-02-19clk: meson: g12a: add support for the SPICC SCLK Source clocksNeil Armstrong
This adds the clocks used for the Amlogic G12A and compatible SoCs SPICC controller to provide a more complete range of frequencies instead of the SPICC internal divider over Xtal. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-02-13clk: meson: gxbb: set audio output clock hierarchyJerome Brunet
The aiu devices peripheral clocks needs the aiu and aiu_glue clocks to operate. Reflect this hierarchy in the gxbb clock tree. Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-02-13clk: meson: gxbb: add the gxl internal dac gateJerome Brunet
Add the ACODEC clock gate to the gxl clk controller driver Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-01-31Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', ↵Stephen Boyd
'clk-amlogic' and 'clk-allwinner' into clk-next - Support dangerous debugfs actions on clks with dead code - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs * clk-debugfs-danger: clk: Add support for setting clk_rate via debugfs * clk-basic-hw: clk: divider: Add support for specifying parents via DT/pointers clk: gate: Add support for specifying parents via DT/pointers clk: mux: Add support for specifying parents via DT/pointers clk: asm9260: Use parent accuracy in fixed rate clk clk: fixed-rate: Document that accuracy isn't a rate clk: fixed-rate: Add clk flags for parent accuracy clk: fixed-rate: Add support for specifying parents via DT/pointers clk: fixed-rate: Document accuracy member clk: fixed-rate: Move to_clk_fixed_rate() to C file clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy() clk: fixed-rate: Convert to clk_hw based APIs clk: gpio: Use DT way of specifying parents * clk-renesas: clk: renesas: Prepare for split of R-Car H3 config symbol dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo clk: renesas: r7s9210: Add SPIBSC clock clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks clk: renesas: Remove use of ARCH_R8A7796 clk: renesas: rcar-gen2: Change multipliers and dividers to u8 * clk-amlogic: clk: clarify that clk_set_rate() does updates from top to bottom clk: meson: meson8b: make the CCF use the glitch-free mali mux clk: meson: pll: Fix by 0 division in __pll_params_to_rate() clk: meson: g12a: fix missing uart2 in regmap table clk: meson: meson8b: use of_clk_hw_register to register the clocks clk: meson: meson8b: don't register the XTAL clock when provided via OF clk: meson: meson8b: change references to the XTAL clock to use [fw_]name clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller dt-bindings: clock: meson8b: add the clock inputs dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding * clk-allwinner: clk: sunxi: a23/a33: Export the MIPI PLL clk: sunxi: a31: Export the MIPI PLL clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock clk: sunxi-ng: r40: Export MBUS clock clk: sunxi: use of_device_get_match_data
2020-01-07clk: meson: meson8b: make the CCF use the glitch-free mali muxMartin Blumenstingl
The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. This fixes a potential hang when changing the GPU frequency at runtime. Fixes: 74e1f2521f16ff ("clk: meson: meson8b: add the GPU clock tree") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-23clk: let init callback return an error codeJerome Brunet
If the init callback is allowed to request resources, it needs a return value to report the outcome of such a request. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-16Merge branch 'v5.5/fixes' into v5.6/driversJerome Brunet
2019-12-16clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel
Some meson pll registers can be initialized with 0 as N value, introducing the following division by 0 when computing rate : UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9 division by zero CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400 Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x14/0x20 dump_stack+0xc4/0x100 ubsan_epilogue+0x14/0x68 __ubsan_handle_divrem_overflow+0x98/0xb8 __pll_params_to_rate+0xdc/0x140 meson_clk_pll_recalc_rate+0x278/0x3a0 __clk_register+0x7c8/0xbb0 devm_clk_hw_register+0x54/0xc0 meson_eeclkc_probe+0xf4/0x1a0 platform_drv_probe+0x54/0xd8 really_probe+0x16c/0x438 driver_probe_device+0xb0/0xf0 device_driver_attach+0x94/0xa0 __driver_attach+0x70/0x108 bus_for_each_dev+0xd8/0x128 driver_attach+0x30/0x40 bus_add_driver+0x1b0/0x2d8 driver_register+0xbc/0x1d0 __platform_driver_register+0x78/0x88 axg_driver_init+0x18/0x20 do_one_initcall+0xc8/0x24c kernel_init_freeable+0x2b0/0x344 kernel_init+0x10/0x128 ret_from_fork+0x10/0x18 This checks if N is null before doing the division. Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt> [jbrunet@baylibre.com: update the comment in above the fix] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 23:27:31 +0000