| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-03-27 | clk: meson8b: add the mplls clocks 0, 1 and 2 | Jerome Brunet |
| 2017-03-27 | clk: meson8b: put dividers and muxes in tables | Jerome Brunet |
| 2017-03-27 | clk: meson: add missing const qualifiers on gate arrays | Jerome Brunet |
| 2017-01-26 | clk: meson8b: fix clk81 register address | Jerome Brunet |
| 2016-09-14 | clk: meson: fix CLKID_GCLK_VENCI_INT typo | Arnd Bergmann |
| 2016-09-14 | meson: clk: Use builtin_platform_driver to simplify the code | Wei Yongjun |
| 2016-09-01 | meson: clk: Add support for clock gates | Alexander Müller |
| 2016-09-01 | clk: meson: Copy meson8b CLKID defines to private header file | Alexander Müller |
| 2016-09-01 | meson: clk: Rename register names according to Amlogic datasheet | Alexander Müller |
| 2016-09-01 | meson: clk: Move register definitions to meson8b.h | Alexander Müller |
| 2016-09-01 | clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention | Alexander Müller |
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