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2013-11-06arc: remove '__init' for setup_processor() and arc_init_IRQ()Chen Gang
They haven't '__init' in definition, but has '__init' in declaration. And normal function start_kernel_secondary() may call setup_processor() which will call arc_init_IRQ(). So need remove '__init' for both of them. The related warning (with allmodconfig): MODPOST vmlinux.o WARNING: vmlinux.o(.text+0x3084): Section mismatch in reference from the function start_kernel_secondary() to the function .init.text:setup_processor() The function start_kernel_secondary() references the function __init setup_processor(). This is often because start_kernel_secondary lacks a __init annotation or the annotation of setup_processor is wrong. Signed-off-by: Chen Gang <gang.chen@asianux.com>
2013-11-06arc: kgdb: add default implementation for kgdb_roundup_cpus()Chen Gang
arc supports kgdb, but need update -- add function kgdb_roundup_cpus(), or can not pass compiling. At present, add the simple generic one just like other architectures(e.g. tile, mips ...). The related error (with allmodconfig): kernel/built-in.o: In function `kgdb_cpu_enter': kernel/debug/debug_core.c:580: undefined reference to `kgdb_roundup_cpus' Signed-off-by: Chen Gang <gang.chen@asianux.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: Fix bogus gcc warning and micro-optimise TLB iteration loopVineet Gupta
------------------>8---------------------- arch/arc/mm/tlb.c: In function ‘do_tlb_overlap_fault’: arch/arc/mm/tlb.c:688:13: warning: array subscript is above array bounds [-Warray-bounds] (pd0[n] & PAGE_MASK)) { ^ ------------------>8---------------------- While at it, remove the usless last iteration of outer loop when reading a TLB SET for duplicate entries. Suggested-by: Mischa Jonker <mjonker@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: Add support for irqflags tracing and lockdepVineet Gupta
Lockdep required a small fix to stacktrace API which was incorrectly unwindign out of __switch_to for the current call frame. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: Reset the value of Interrupt Priority RegisterVineet Gupta
In case bootloader has changed the priority of one/more IRQ lines Reported-by: Noam Camus <noamc@ezchip.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: Reduce #ifdef'ery for unaligned access emulationVineet Gupta
Emulation not enabled is treated as if the fixup failed, so no need for special #ifdef checks. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: Change calling convention of do_page_fault()Vineet Gupta
switch the args (address, pt_regs) to match with all the other "C" exception handlers. This removes the awkwardness in EV_ProtV for page fault vs. unaligned access. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: cacheflush optim - PTAG can be loop invariant if V-P is constVineet Gupta
Line op needs vaddr (indexing) and paddr (tag match). For page sized flushes (V-P const), each line op will need a different index, but the tag bits wil remain constant, hence paddr can be setup once outside the loop. This improves select LMBench numbers for Aliasing dcache where we have more "preventive" cache flushing. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 3.11-rc7- Linux 3.11.0- 80 4.66 8.88 69.7 112. 268. 8.60 28.0 3489 13.K 27.K # Non alias ARC700 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 68.6 98.5 271. 8.58 28.1 4160 15.K 32.K # Aliasing 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 69.8 99.4 270. 8.73 27.5 3880 15.K 31.K # PTAG loop Inv Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: cacheflush refactor #3: Unify the {d,i}cache flush leaf helpersVineet Gupta
With Line length being constant now, we can fold the 2 helpers into 1. This allows applying any optimizations (forthcoming) to single place. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: cacheflush refactor #2: I and D caches lines to have same sizeVineet Gupta
Having them be different seems an obscure configuration. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: cacheflush refactor #1: push aux reg ascertaining into leaf routineVineet Gupta
ARC dcache supports 3 ops - Inv, Flush, Flush-n-Inv. The programming model however provides 2 commands FLUSH, INV. INV will either discard or flush-n-discard (based on DT_CTRL bit) The leaf helper __dc_line_loop() used to take the AUX register (corresponding to the 2 commands). Now we push that to within the helper, paving way for code consolidations to follow. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: use __weak instead of __attribute__((weak))Vineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06ARC: Annotate some functions as staticVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-11-06arc: Replace __get_cpu_var usesChristoph Lameter
__get_cpu_var() is used for multiple purposes in the kernel source. One of them is address calculation via the form &__get_cpu_var(x). This calculates the address for the instance of the percpu variable of the current processor based on an offset. Other use cases are for storing and retrieving data from the current processors percpu area. __get_cpu_var() can be used as an lvalue when writing data or on the right side of an assignment. __get_cpu_var() is defined as : #define __get_cpu_var(var) (*this_cpu_ptr(&(var))) __get_cpu_var() always only does an address determination. However, store and retrieve operations could use a segment prefix (or global register on other platforms) to avoid the address calculation. this_cpu_write() and this_cpu_read() can directly take an offset into a percpu area and use optimized assembly code to read and write per cpu variables. This patch converts __get_cpu_var into either an explicit address calculation using this_cpu_ptr() or into a use of this_cpu operations that use the offset. Thereby address calcualtions are avoided and less registers are used when code is generated. At the end of the patchset all uses of __get_cpu_var have been removed so the macro is removed too. The patchset includes passes over all arches as well. Once these operations are used throughout then specialized macros can be defined in non -x86 arches as well in order to optimize per cpu access by f.e. using a global register that may be set to the per cpu base. Transformations done to __get_cpu_var() 1. Determine the address of the percpu instance of the current processor. DEFINE_PER_CPU(int, y); int *x = &__get_cpu_var(y); Converts to int *x = this_cpu_ptr(&y); 2. Same as #1 but this time an array structure is involved. DEFINE_PER_CPU(int, y[20]); int *x = __get_cpu_var(y); Converts to int *x = this_cpu_ptr(y); 3. Retrieve the content of the current processors instance of a per cpu variable. DEFINE_PER_CPU(int, u); int x = __get_cpu_var(y) Converts to int x = __this_cpu_read(y); 4. Retrieve the content of a percpu struct DEFINE_PER_CPU(struct mystruct, y); struct mystruct x = __get_cpu_var(y); Converts to memcpy(this_cpu_ptr(&x), y, sizeof(x)); 5. Assignment to a per cpu variable DEFINE_PER_CPU(int, y) __get_cpu_var(y) = x; Converts to this_cpu_write(y, x); 6. Increment/Decrement etc of a per cpu variable DEFINE_PER_CPU(int, y); __get_cpu_var(y)++ Converts to this_cpu_inc(y) Acked-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Christoph Lameter <cl@linux.com>
2013-11-05arm64: compat: Clear the IT state independent of the 32-bit ARM or Thumb-2 modeT.J. Purtell
The ARM architecture reference specifies that the IT state bits in the PSR must be all zeros in ARM mode or behavior is unspecified. If an ARM function is registered as a signal handler, and that signal is delivered inside a block of instructions following an IT instruction, some of the instructions at the beginning of the signal handler may be skipped if the IT state bits of the Program Status Register are not cleared by the kernel. Signed-off-by: T.J. Purtell <tj@mobisocial.us> [catalin.marinas@arm.com: code comment and commit log updated] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-11-05arm64: Use 42-bit address space with 64K pagesCatalin Marinas
This patch expands the VA_BITS to 42 when the 64K page configuration is enabled allowing 2TB kernel linear mapping. Linux still uses 2 levels of page tables in this configuration with pgd now being a full page. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
2013-11-05arm64: module: ensure instruction is little-endian before manipulationWill Deacon
Relocations that require an instruction immediate to be re-encoded must ensure that the instruction pattern is represented in a little-endian format for the manipulation code to work correctly. This patch converts the loaded instruction into native-endianess prior to encoding and then converts back to little-endian byteorder before updating memory. Signed-off-by: Will Deacon <will.deacon@arm.com> Tested-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-11-05arm64: defconfig: Enable CONFIG_PREEMPT by defaultCatalin Marinas
This way we can spot early bugs when just testing with the default config. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-11-05arm64: fix access to preempt_count from assembly codeMarc Zyngier
preempt_count is defined as an int. Oddly enough, we access it as a 64bit value. Things become interesting when running a BE kernel, and looking at the current CPU number, which is stored as an int next to preempt_count. Like in a per-cpu interrupt handler, for example... Using a 32bit access fixes the issue for good. Cc: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-11-04arm64: move enabling of GIC before CPUs are set onlineMarc Zyngier
Commit 53ae3acd (arm64: Only enable local interrupts after the CPU is marked online) moved the enabling of the GIC after the CPUs are marked online. This has some interesting effect: [...] [<ffffffc0002eefd8>] gic_raise_softirq+0xf8/0x160 [<ffffffc000088f58>] smp_send_reschedule+0x38/0x40 [<ffffffc0000c8728>] resched_task+0x84/0xc0 [<ffffffc0000c8cdc>] check_preempt_curr+0x58/0x98 [<ffffffc0000c8d38>] ttwu_do_wakeup+0x1c/0xf4 [<ffffffc0000c8f90>] ttwu_do_activate.constprop.84+0x64/0x70 [<ffffffc0000cad30>] try_to_wake_up+0x1d4/0x2b4 [<ffffffc0000cae6c>] default_wake_function+0x10/0x18 [<ffffffc0000c5ca4>] __wake_up_common+0x60/0xa0 [<ffffffc0000c7784>] complete+0x48/0x64 [<ffffffc000088bec>] secondary_start_kernel+0xe8/0x110 [...] Here, we end-up calling gic_raise_softirq without having initialized the interrupt controller for this CPU. While this goes unnoticed with GICv2 (the distributor is always accessible), it explodes with GICv3. The fix is to move the call to notify_cpu_starting before we set the secondary CPU online. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-11-04arm64: use generic RW_DATA_SECTION macro in linker scriptMark Salter
The .data section in the arm64 linker script currently lacks a definition for page-aligned data. This leads to a .page_aligned section being placed between the end of data and start of bss. This patch corrects that by using the generic RW_DATA_SECTION macro which includes support for page-aligned data. Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-11-04MIPS: Random whitespace clean-upsMaciej W. Rozycki
Another whitespace clean-up, this removes tabs from between sentences in some comments. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6103/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-11-04s390/mm,tlb: correct tlb flush on page table upgradeMartin Schwidefsky
The IDTE instruction used to flush TLB entries for a specific address space uses the address-space-control element (ASCE) to identify affected TLB entries. The upgrade of a page table adds a new top level page table which changes the ASCE. The TLB entries associated with the old ASCE need to be flushed and the ASCE for the address space needs to be replaced synchronously on all CPUs which currently use it. The concept of a lazy ASCE update with an exception handler is broken. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2013-11-04Merge branch 'perf/urgent' into perf/core to fix conflictsIngo Molnar
Conflicts: tools/perf/bench/numa.c Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-11-03Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds
Pull MIPS fixes from Ralf Baechle: "Three fixes across arch/mips with the most complex one being the GIC interrupt fix - at nine lines still not monster. I'm confident this are the final MIPS patches even if there should go for an rc8" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MIPS: ralink: fix return value check in rt_timer_probe() MIPS: malta: Fix GIC interrupt offsets MIPS: Perf: Fix 74K cache map
2013-11-02ARC: Incorrect mm reference used in vmalloc fault handlerVineet Gupta
A vmalloc fault needs to sync up PGD/PTE entry from init_mm to current task's "active_mm". ARC vmalloc fault handler however was using mm. A vmalloc fault for non user task context (actually pre-userland, from init thread's open for /dev/console) caused the handler to deref NULL mm (for mm->pgd) The reasons it worked so far is amazing: 1. By default (!SMP), vmalloc fault handler uses a cached value of PGD. In SMP that MMU register is repurposed hence need for mm pointer deref. 2. In pre-3.12 SMP kernel, the problem triggering vmalloc didn't exist in pre-userland code path - it was introduced with commit 20bafb3d23d108bc "n_tty: Move buffers into n_tty_data" Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Gilad Ben-Yossef <gilad@benyossef.com> Cc: Noam Camus <noamc@ezchip.com> Cc: stable@vger.kernel.org #3.10 and 3.11 Cc: Peter Hurley <peter@hurleysoftware.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-11-01Merge branch 'perf-urgent-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fixes from Ingo Molnar: "Two fixes: - Fix 'NMI handler took too long to run' false positives [ Genuine NMI overhead speedups will come for v3.13, this commit only fixes a measurement bug ] - Fix perf ring-buffer missed barrier causing (rare) ring-buffer data corruption on ppc64" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86: Fix NMI measurements perf: Fix perf ring buffer memory ordering
2013-11-01Merge branch 'linus' into sched/coreIngo Molnar
Resolve cherry-picking conflicts: Conflicts: mm/huge_memory.c mm/memory.c mm/mprotect.c See this upstream merge commit for more details: 52469b4fcd4f Merge branch 'core-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Signed-off-by: Ingo Molnar <mingo@kernel.org>
2013-10-31Merge tag 'dt-3.13-5' of git://git.infradead.org/linux-mvebu into next/dtOlof Johansson
From Jason Cooper: - add the Openblocks A7 board - add Netgear ReadyNAS 104 board * tag 'dt-3.13-5' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Add Netgear ReadyNAS 104 board ARM: kirkwood: add support for OpenBlocks A7 platform Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-31Merge branch 'bcm/dt' into next/dtOlof Johansson
A handful of DT updates from Christian Daudt for the broadcom mobile platforms, including their rename of the platform to BCM_MOBILE to keep BCM for the vendor-level options. * bcm/dt: ARM: dts: bcm11351: Use GIC/IRQ defines for sdio interrupts ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx) ARM: dts: bcm281xx: Add card detect GPIO ARM: dts: rename ARCH_BCM to ARCH_BCM_MOBILE (dt) ARM: bcm281xx: Add device node for the GPIO controller Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-31ARM: dts: bcm11351: Use GIC/IRQ defines for sdio interruptsMatt Porter
Trivial patch to make use of GIC/IRQ defines on the bcm11351 sdio interrupt properties. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-31ARM: dts: bcm: Add missing UARTs for bcm11351 (bcm281xx)Tim Kryger
This adds in three more UARTs that were not declared earlier. Signed-off-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-31ARM: dts: bcm281xx: Add card detect GPIOMarkus Mayer
Register GPIO 14 as card detect interrupt for the SD card slot. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Signed-off-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-31ARM: dts: rename ARCH_BCM to ARCH_BCM_MOBILE (dt)Christian Daudt
Currently ARCH_BCM has been used for Broadcom Mobile V7 based SoCs. In order to allow other Broadcom SoCs to also use mach-bcm directory and files, this patch renames the original ARCH_BCM to ARCH_BCM_MOBILE, and uses ARCH_BCM to define any Broadcom chip residing in mach-bcm directory. Signed-off-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-31ARM: bcm281xx: Add device node for the GPIO controllerMarkus Mayer
Add the GPIO controller device node for the Broadcom bcm281xx family of mobile SoCs. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-31arm64: Slightly improve the warning on CPU0 enable-methodCatalin Marinas
Commit e8765b265a69 (arm64: read enable-method for CPU0) introduced checks for the enable method on CPU0 (to be later used with CPU suspend). However, if the kernel is compiled for UP and a DT file is used with a method like 'spin-table', Linux complains about 'invalid enable method'. This patch turns it into an 'unsupported enable method' warning. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2013-10-31s390/mm: page_table_realloc returns failureDominik Dingel
There is a possible race between setting has_pgste and reallocation of the page_table, change the order to fix this. Also page_table_alloc_pgste can fail, in that case we need to backpropagte this as -ENOMEM to the caller of page_table_realloc. Based on a patch by Christian Borntraeger <borntraeger@de.ibm.com>. Reviewed-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2013-10-31ARM: mvebu: Add Netgear ReadyNAS 104 boardArnaud Ebalard
Main hardware parts of the (Armada 370 based) NETGEAR ReadyNAS 104 are supported by mainline kernel (USB 3.0 rear ports, USB 2.0 front port, Gigabit controller and PHYs, serial port, LEDs, buttons, SATA ports, G762 fan controller) and referenced in provided .dts file. Some additonal work remains for: - Intersil ISL12057 I2C RTC and Alarm chip: working driver but needs to be splitted for submission of RTC part first; - Front LCD (Winstar 1602G): driver needs to be written - Armada NAND controller (to access onboard 128MB of NAND): support being pushed by @free-electrons people - 4 front SATA LEDs controlled via GPIO brought by NXP PCA9554: driver is available upstream. Not referenced/tested yet. but the device is usable w/o those. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-31MIPS: ralink: fix return value check in rt_timer_probe()Wei Yongjun
In case of error, the function devm_request_and_ioremap() returns NULL pointer not ERR_PTR(). Fix it by using devm_ioremap_resource() instead of devm_request_and_ioremap(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: John Crispin <blogic@openwrt.org> Cc: grant.likely@linaro.org Cc: rob.herring@calxeda.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6098/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-31s390: allow to set gcc -mtune flagHeiko Carstens
Add a new Kconfig choice group which allows to configure how gcc should tune the generated code (via -mtune option). By default the -mtune parameter will match the -march parameter. This is a rather large patch, but I wouldn't know how to make this shorter unfortunately. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2013-10-31s390/percpu: remove this_cpu_xor() implementationHeiko Carstens
this_cpu_xor() will be removed tree wide during the next merge window. To avoid merge conflicts s390's removal comes via the s390 tree. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2013-10-31s390/vtime: correct idle time calculationMartin Schwidefsky
Use the ACCESS_ONCE macro for both accesses to idle->sequence in the loops to calculate the idle time. If only one access uses the macro, the compiler is free to cache the value for the second access which can cause endless loops. Cc: stable@vger.kernel.org # 3.6+ Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2013-10-31s390/time: fix get_tod_clock_ext inline assemblyMartin Schwidefsky
The get_tod_clock_ext inline assembly does not specify its output operands correctly. This can cause incorrect code to be generated. Cc: stable@vger.kernel.org # 3.12 Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2013-10-30ARM: bcm281xx: Add ARCH_BCM_MOBILE to bcm configChristian Daudt
This patch (re)adds ARCH_BCM_MOBILE option to bcm_defconfig which was accidentally removed by commit 2d58b26550ad ('ARM: bcm_defconfig: Run "make savedefconfig"') Signed-off-by: Christian Daudt <bcm@fixthebug.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-30ARM: tegra: fix Tegra114 IOMMU register addressHiroshi Doyu
The IOMMU node's reg property contains completely bogus values! Somehow, this had no practical effect, despite the fact the IOMMU driver appears to be writing to those registers. I suppose that since no HW modules is actually at that address, the writes simply had no effect. Note that I'm not CCing stable here, even though the problem exists as far back as v3.9, simply because this patch doesn't fix any observed issue, and I don't want to run the risk of suddenly writing to some registers and causing a regression. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, wrote commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-30Merge branch 'akpm' (fixes from Andrew Morton)Linus Torvalds
Merge three fixes from Andrew Morton. * emailed patches from Andrew Morton <akpm@linux-foundation.org>: memcg: use __this_cpu_sub() to dec stats to avoid incorrect subtrahend casting percpu: fix this_cpu_sub() subtrahend casting for unsigneds mm/pagewalk.c: fix walk_page_range() access of wrong PTEs
2013-10-30percpu: fix this_cpu_sub() subtrahend casting for unsignedsGreg Thelen
this_cpu_sub() is implemented as negation and addition. This patch casts the adjustment to the counter type before negation to sign extend the adjustment. This helps in cases where the counter type is wider than an unsigned adjustment. An alternative to this patch is to declare such operations unsupported, but it seemed useful to avoid surprises. This patch specifically helps the following example: unsigned int delta = 1 preempt_disable() this_cpu_write(long_counter, 0) this_cpu_sub(long_counter, delta) preempt_enable() Before this change long_counter on a 64 bit machine ends with value 0xffffffff, rather than 0xffffffffffffffff. This is because this_cpu_sub(pcp, delta) boils down to this_cpu_add(pcp, -delta), which is basically: long_counter = 0 + 0xffffffff Also apply the same cast to: __this_cpu_sub() __this_cpu_sub_return() this_cpu_sub_return() All percpu_test.ko passes, especially the following cases which previously failed: l -= ui_one; __this_cpu_sub(long_counter, ui_one); CHECK(l, long_counter, -1); l -= ui_one; this_cpu_sub(long_counter, ui_one); CHECK(l, long_counter, -1); CHECK(l, long_counter, 0xffffffffffffffff); ul -= ui_one; __this_cpu_sub(ulong_counter, ui_one); CHECK(ul, ulong_counter, -1); CHECK(ul, ulong_counter, 0xffffffffffffffff); ul = this_cpu_sub_return(ulong_counter, ui_one); CHECK(ul, ulong_counter, 2); ul = __this_cpu_sub_return(ulong_counter, ui_one); CHECK(ul, ulong_counter, 1); Signed-off-by: Greg Thelen <gthelen@google.com> Acked-by: Tejun Heo <tj@kernel.org> Acked-by: Johannes Weiner <hannes@cmpxchg.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-10-30Merge tag 'bcm-for-3.13-soc2' of git://github.com/broadcom/bcm11351 into ↵Olof Johansson
next/soc From Christian Daudt, BCM changes for 3.13/soc. Mostly cleanups and renaming of kernel config options, pushing down the mobile platforms one level in the naming scheme, keeping ARCH_BCM as a wider family config option. * tag 'bcm-for-3.13-soc2' of git://github.com/broadcom/bcm11351: ARM: bcm_defconfig: Run "make savedefconfig" ARM: bcm281xx: Add ARCH Timers to config rename ARCH_BCM to ARCH_BCM_MOBILE (mach-bcm) ARM: bcm281xx: more descriptive machine string ARM: bcm281xx: Enable GPIO driver Signed-off-by: Olof Johansson <olof@lixom.net>
2013-10-30ARM: kirkwood: add support for OpenBlocks A7 platformThomas Petazzoni
The OpenBlocks A7 board is designed and sold by PlatHome, and based on a Kirkwood 6283 Marvell SoC. It is quite similar to the OpenBlocks A6 already supported in the kernel, with the following main differences: - The A6 uses a RTC on I2C, while the A7 uses the internal SoC RTC. - The A6 has one Ethernet port, while the A7 has two Ethernet ports - The A6 has only one USB port, while the A7 integrates a USB hub, which provides two front-side USB port, and an internal USB port as well. - The A6 has 512 MB of RAM, while the A7 has 1 GB of RAM. - Slightly different GPIOs for some functions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-10-30Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull KVM fixes from Paolo Bonzini: "Fixes for the 3.12 debugfs problem - removing the duplicate directory name, and using a better the error code" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: use a more sensible error number when debugfs directory creation fails KVM: Fix modprobe failure for kvm_intel/kvm_amd
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