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No reason I can think of of making them default y Most people don't have
the hardware and with default y they just pollute lots of configs during
make oldconfig.
Signed-off-by: Andi Kleen <ak@suse.de>
Acked-by: Jeff Garzik <jeff@garzik.org>
Acked-by: "Nelson, Shannon" <shannon.nelson@intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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This patch removes the dead X86_REMOTE_DEBUG option.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
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This patch merges the x86_64 EARLY_PRINTK option into the i386 one.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
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node0_bdata and paddr_to_nid() can become static.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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This patch removes the unused EXPORT_SYMBOL(machine_id).
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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This patch renames the 4 symbols iommu_hole_init(), iommu_aperture,
iommu_aperture_allowed, iommu_aperture_disabled. All these symbols are only
used for the GART implementation of IOMMUs.
It adds and additional gart_ prefix to them.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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This patch makes some functions and variables static in pci-gart_64.c which are
not used somewhere else.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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This patch renames the IOMMU config option to GART_IOMMU because in fact it
means the GART and not general support for an IOMMU on x86.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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This patch renames the include file asm-x86/iommu.h to asm-x86/gart.h to make
clear to which IOMMU implementation it belongs. The patch also adds "GART" to
the Kconfig line.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Additional CPUID strings (sse4_1, sse4_2, sse5, skinit, wdt); fix the
positioning of the AMD ecx strings (cr8_legacy was duplicated under
two different names, so the alignment of all the other strings were
off by one.)
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (34 commits)
[MIPS] tb0219: Update copyright message.
[MIPS] MT: Fix bug in multithreaded kernels.
[MIPS] Alchemy: Remove CONFIG_TS_AU1X00_ADS7846 from defconfigs.
Author: Ralf Baechle <ralf@linux-mips.org>
[MIPS] sb1250: Enable GenBus IDE in defconfig.
[MIPS] vmlinux.ld.S: correctly indent .data section
[MIPS] c-r3k: Implement flush_cache_range()
[MIPS] Store sign-extend register values for PTRACE_GETREGS
[MIPS] Alchemy: Register platform devices
[MIPS] Add len and addr validation for MAP_FIXED mappings.
[MIPS] IRIX: Fix off-by-one error in signal compat code.
[MIPS] time: Replace plat_timer_setup with modern APIs.
[MIPS] time: Fix cut'n'paste bug in Sibyte clockevent driver.
[MIPS] time: Make c0_compare_int_usable faster
[MIPS] time: Fix cevt-r4k.c for 64-bit kernel
[MIPS] Sibyte: Delete {sb1250,bcm1480}_steal_irq().
[MIPS] txx9tmr clockevent/clocksource driver
[MIPS] Add mips_hpt_frequency check to mips_clockevent_init().
[MIPS] IP32: Fixes after interrupt renumbering.
[MIPS] IP27: Fix slice logic to work for arbitrary number of slices.
...
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This reverts commit 2e1c49db4c640b35df13889b86b9d62215ade4b6.
First off, testing in Fedora has shown it to cause boot failures,
bisected down by Martin Ebourne, and reported by Dave Jobes. So the
commit will likely be reverted in the 2.6.23 stable kernels.
Secondly, in the 2.6.24 model, x86-64 has now grown support for
SPARSEMEM_VMEMMAP, which disables the relevant code anyway, so while the
bug is not visible any more, it's become invisible due to the code just
being irrelevant and no longer enabled on the only architecture that
this ever affected.
Reported-by: Dave Jones <davej@redhat.com>
Tested-by: Martin Ebourne <fedora@ebourne.me.uk>
Cc: Zou Nan hai <nanhai.zou@intel.com>
Cc: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Acked-by: Andy Whitcroft <apw@shadowen.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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When GDB writes a breakpoint into address area of inferior process the
kernel needs to invalidate the modified memory in the inferior which
is done by calling flush_cache_page which in turns calls
r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC
kernel via r4k_on_each_cpu().
As the VSMP and SMTC SMP kernels for 34K are running on a single shared
caches it is possible to get away without interprocessor function calls.
This optimization is implemented in r4k_on_each_cpu, so
local_r4k_flush_cache_page is only ever called on the local CPU.
This is where the following code in local_r4k_flush_cache_page() strikes:
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (cpu_context(smp_processor_id(), mm) == 0)
return;
On VSMP and SMTC had a function of cpu_context() for each CPU(TC).
So in case another CPU than the CPU executing local_r4k_cache_flush_page
has not accessed the mm but one of the other CPUs has there may be data
to be flushed in the cache yet local_r4k_cache_flush_page will falsely
return leaving the I-cache inconsistent for the breakpoint.
While the issue was discovered with GDB it also exists in
local_r4k_flush_cache_range() and local_r4k_flush_cache().
Fixed by introducing a new function has_valid_asid which on MT kernels
returns true if a mm is active on any processor in the system.
This is relativly expensive since for memory acccesses in that loop
cache misses have to be assumed but it seems the most viable solution
for 2.6.23 and older -stable kernels.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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[MIPS] MSP71xx: Fix bitrot.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Enable the onboard GenBus IDE interface in the default configuration.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Contrary to the belief of some, the R3000 and related processors did have
caches, both a data and an instruction cache. Here is an implementation
of r3k_flush_cache_page(), which is the processor-specific back-end for
flush_cache_range(), done according to the spec in
Documentation/cachetlb.txt.
While at it, remove an unused local function: get_phys_page(), do some
trivial formatting fixes and modernise debugging facilities.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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A comment on ptrace_getregs() states "Registers are sign extended to
fill the available space." but it is not true. Fix code to match the
comment. Also fix casts on each caller to get rid of some warnings.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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This patch separates the platform devices registration for the MTX-1
specific devices: GPIO leds and watchdog.
[Minor fixup and formatting change -- Ralf]
Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Mmap with MAP_FIXED was not validating the addr and len parameters. This
leads to the failure of GCC's gcc.c-torture/execute/loop-2[fg].c testcases
when using the o32 ABI on a 64 bit kernel.
These testcases try to mmap 65536 bytes at 0x7fff8000 and then access all
the memory. In 2.6.18 and 2.6.23.1 (and likely other versions as well)
the kernel maps the requested memory, but since half of it is above
0x80000000 a SIGBUS is generated when it is accessed.
This patch moves the len validation above the MAP_FIXED processing so that
it is always validated. It also adds validation to the addr parameter for
MAP_FIXED mappings.
Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Based on original patch by Roel Kluin <12o3l@tiscali.nl>.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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plat_timer_setup is no longer getting called.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Try increasingly longer time periods starting of at 0x10 cycles. This
should be fast on hardware and work nicely with emulators.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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The expression "(long)(read_c0_count() - cnt)" can never be a negative
value on 64-bit kernel. Cast to "int" before comparison.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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They break the timer interrupt initialization and only seem to be a kludge
for initialization happening in the wrong order. Further testing done by
Thiemo confirms the suspicion that the other invocations also seem to have
useless.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Convert jmr3927_clock_event_device to more generic
txx9tmr_clock_event_device which supports one-shot mode. The
txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer
interrupt was not available.
Convert jmr3927_hpt_read to txx9_clocksource driver which does not
depends jiffies anymore. The txx9_clocksource itself can be used for
TX49, but normally TX49 uses higher precision clocksource_mips.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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And general untangling.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
to handle the alternate timer interrupt of the RM9000.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Since the cp0 compare interrupt handler isn't initialized by the time
plat_time_init is called don't set IE_IRQ5 anymore, cevt-r4k.c will do
that a little later itself.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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The only thing it used to do is now done by cevt-r4k.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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The old plat_timer_setup hook is no longer getting called so the Alchemy
time initialization was getting skipped.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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This subtle difference makes ELF overlays work.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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clockevent_delta2ns() use the shift and mult value, so
clockevent_set_clock() should be called first.
Pointed out by Atsushi Nemoto.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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set_next_event() and set_mode() are always called with interrupt disabled.
irqsave and irqrestore are not necessary for spinlock.
Pointed out by Atsushi Nemoto.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Modify the SMTC initialization code to allow boot-time specification not
only of how many VPEs and TCs to use, but also how many TCs out of the
allowed pool are to be bound to VPE 0. The new boot option is "vpe0tcs=N",
where N is an integer. Using it in combination with the existing options
allows arbitrary assignments across the 2 VPEs of a 34K. e.g. "maxtcs=3
vpe0tcs=1" forces VPE0 to have 1 TC, while VPE1 has 2, and "maxtcs=4
vpe0tcs=3" forces VPE0 to have 3 TCs, while VPE1 gets 1. If no vpe0tcs
option is specified, the traditional algorithm of evenly dividing TCs
between available VPEs, with the odd "slop" going to VPE0, is retained.
The reason for doing this is to allow a finer balancing of TCs which can
handle I/O interrupts on Malta (those on VPE 0) and those which cannot.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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* 'sg' of git://git.kernel.dk/linux-2.6-block:
Correction of "Update drivers to use sg helpers" patch for IMXMMC driver
sg_init_table() should use unsigned loop index variable
sg_last() should use unsigned loop index variable
Initialise scatter/gather list in sg driver
Initialise scatter/gather list in ata_sg_setup
x86: fix pci-gart failure handling
SG: s390-scsi: missing size parameter in zfcp_address_to_sg()
SG: clear termination bit in sg_chain()
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Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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arch/i386/{Kconfig,Makefile}.cpu got moved
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Don't undef __i386__/__x86_64__ in uml anymore, make sure that (few) places
that required adjusting the ifdefs got those.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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blk_rq_map_sg doesn't initialize sg->dma_address/length to zero
anymore. Some low level drivers reuse sg lists without initializing so
IOMMUs might get non-zero dma_address/length. If map_sg fails, we need
pass the number of the mapped entries to gart_unmap_sg.
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
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