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2010-07-05MIPS: Tracing: Fix argument passing of the 32bit support with gcc 4.5Wu Zhangjin
As documented in the GCC 4.5 docs [1] -mmcount-ra-address uses register $12 to pass the stack offset of the return address to the _mcount function. On 64-bit kernels $12 is t0 but in 32-bit kernels it is t4 so we need to use $12 instead of t0 here to be correct for both kernel types. [1] GCC documentation: MIPS Options http://gcc.gnu.org/onlinedocs/gcc/MIPS-Options.html Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1227/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Tracing: Cleanup commentsWu Zhangjin
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1225/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Tracing: Cleanup the arguments passing of prepare_ftrace_returnWu Zhangjin
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1226/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Tracing: Merge adjacent #ifdefs with same condition.Wu Zhangjin
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: AR7, BCM63xx: fix gpio_to_irq() return valueYoichi Yuasa
The return value of gpio_to_irq() is not a pointer but an integer. Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1280/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Restore signalling NaN behaviour for abs.[sd]Chris Dearman
Atsushi Nemoto <anemo@mba.ocn.ne.jp> spotted that this had been incorrectly removed in a previous patch Signed-off-by: Chris Dearman <chris@mips.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1213/ Tested-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Loongson: CS5536: Fix ISA supportWu Zhangjin
The function _wrmsr() called by divil_lbar_disable()/enable() should be called with the offset as the argument. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Zhang Le <r0bertz@gentoo.org> Patchwork: http://patchwork.linux-mips.org/patch/1252/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Loongson: Add a missing break statement in CS5536 IDE codeWu Zhangjin
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Zhang Le <r0bertz@gentoo.org> Cc: Hu Hongbing <huhb@lemote.com> Patchwork: http://patchwork.linux-mips.org/patch/1251/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: Loongson: CS5536: Add missing RDMSRs for IDE and USBWu Zhangjin
Add several missing RDMSRs for IDE and USB are missing to avoid the agressive modification of the high 32 bits of the MSR. Without this patch some usb devices may fail after printing "reset ehci host ....." when reading the partition information. Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Zhang Le <r0bertz@gentoo.org> Cc: Hu Hongbing <huhb@lemote.com> Patchwork: http://patchwork.linux-mips.org/patch/1250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: AR7: Fix typo in ar7.hFlorian Fainelli
This fixes a typo on the AR7_RESET_PERIPHERAL define. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05MIPS: AR7: Use correct UART port typeFlorian Fainelli
PORT_AR7 has the correct TRIG flag (UART_FCR_R_TRIG_00) as well as UART_CAP_AFE being set. This fixes UART on TNETD7300 revision 0x02, which would otherwise mangle some characters, no side effects on other revisions. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1246/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-07-05rbtree: Undo augmented trees performance damage and regressionPeter Zijlstra
Reimplement augmented RB-trees without sprinkling extra branches all over the RB-tree code (which lives in the scheduler hot path). This approach is 'borrowed' from Fabio's BFQ implementation and relies on traversing the rebalance path after the RB-tree-op to correct the heap property for insertion/removal and make up for the damage done by the tree rotations. For insertion the rebalance path is trivially that from the new node upwards to the root, for removal it is that from the deepest node in the path from the to be removed node that will still be around after the removal. [ This patch also fixes a video driver regression reported by Ali Gholami Rudi - the memtype->subtree_max_end was updated incorrectly. ] Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: Venkatesh Pallipadi <venki@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Tested-by: Ali Gholami Rudi <ali@rudi.ir> Cc: Fabio Checconi <fabio@gandalf.sssup.it> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> LKML-Reference: <1275414172.27810.27961.camel@twins> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-07-05ARM: SAMSUNG: Fix on wrong function name for S5PV210 sdhci0Hyuk Lee
This patch fixes on wrong function name in include/plat/sdhci.h for Samsung. The 's5pc100_default_sdhci0()' function should be chnaged to 's5pv210_default_sdhci0()'. Because 's5pv210_default_sdhci0()' must be pair. Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-07-05ARM: S5P6442: Fix PLL setting announce message.Thomas Abraham
The S5P6442 PLL setting announce message incorrectly displays S5P6440 as the SoC. Change it to S5P6442. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-07-05ARM: SAMSUNG: Fix build without SDHCI controllers for S3C64XXMarek Szyprowski
This patch fixes the following compilation problem if only NCP machine is selected: arch/arm/mach-s3c64xx/s3c6410.c: In function 's3c6410_map_io': arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function 's3c6410_default_sdhci2' And also adds missed 's3c6400_default_sdhci2'. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix and added comments] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-07-05ARM: S5PV210: Correct clock register propertiesMyungJoo Ham
1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were defined incorrectly. 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc, sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their twins defined in struct clk init_clocks_disable[] and struct clk init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK register to avoid the duplicated clock problem described below. NOTE: Duplicated Clock Problem Please note that each clock definition should access different control register; otherwise, the system may suffer lockups. For example, if we have two clock definitions "a" and "b" which access the same register (and the shift value). Then, when we do: module A clk = clk_get("a"); clk->clk_enable(clk); module B (context switch) clk = clk_get("b"); clk->clk_enable(clk); do something with clk. clk->clk_disable(clk); module A (context switch) do something with clk * At this point, the system may hang. Therefore, there should be no clock definitions with the same contol register/shift. If we need to create "aliases", then, creating child clocks sharing the clock should be fine. 3. Corrected other sclk_* shift values and access registers. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title and message fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-07-05ARM: S5P: Bug fix on external interrupt for S5P SoCsBoojin Kim
This patch fixes bug on eint type set function, s5p_irq_eint_set_type(). In the IRQ_TYPE_EDGE_FALLING case, S5P_EXTINT_FALLEDGE is right instead of S5P_EXTINT_RISEEDGE Signed-off-by: Boojin Kim <boojin.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2010-07-04Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds
* master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6205/1: perf: ensure counter delta is treated as unsigned ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220 ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220 ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB section ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB section ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMP ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXA [ARM] pxa/mioa701: fix camera regression [ARM] pxa/z2: fix flash layout to final version [ARM] pxa/z2: fix missing include in battery driver [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.h
2010-07-04Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf, x86: Fix incorrect branches event on AMD CPUs perf tools: Fix find tids routine by excluding "." and ".." x86: Send a SIGTRAP for user icebp traps
2010-07-04ARM: 6205/1: perf: ensure counter delta is treated as unsignedWill Deacon
Hardware performance counters on ARM are 32-bits wide but atomic64_t variables are used to represent counter data in the hw_perf_event structure. The armpmu_event_update function right-shifts a signed 64-bit delta variable and adds the result to the event count. This can lead to shifting in sign-bits if the MSB of the 32-bit counter value is set. This results in perf output such as: Performance counter stats for 'sleep 20': 18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000 7783773 instructions # 0.000 IPC 465 context-switches 161 page-faults 1172393 branches 20.154242147 seconds time elapsed This patch ensures that the delta value is treated as unsigned so that the right shift sets the upper bits to zero. Cc: <stable@kernel.org> Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-03perf, x86: Fix incorrect branches event on AMD CPUsVince Weaver
While doing some performance counter validation tests on some assembly language programs I noticed that the "branches:u" count was very wrong on AMD machines. It looks like the wrong event was selected. Signed-off-by: Vince Weaver <vweaver1@eecs.utk.edu> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: <stable@kernel.org> LKML-Reference: <alpine.DEB.2.00.1007011526010.23160@cl320.eecs.utk.edu> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-07-02ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220Catalin Marinas
RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-02ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220Catalin Marinas
RealView boards with certain revisions of the L220 cache controller (ARM11* processors only) may have issues (hardware deadlock) with the recent changes to the mb() barrier implementation (DSB followed by an L2 cache sync). The patch redefines the RealView ARM11MPCore mandatory barriers without the outer_sync() call. Cc: <stable@kernel.org> Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01Merge branch 'release' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6 * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] Fix spinaphore down_spin()
2010-07-01Merge branch 'imx-for-2.6.35' of git://git.pengutronix.de/git/imx/linux-2.6Russell King
2010-07-01Merge branch 'fix' of ↵Russell King
git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
2010-07-01ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMUWill Deacon
CPU performance event counters on v7 cores will only operate if either the NIDEN or DBGEN signals are driven high. For the OMAP3 platform, these signals are driven low by default but DBGEN can be asserted by selecting the OMAP3_EMU Kconfig option, which enables the virtual clock for hardware debugging peripherals. Acked-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01ARM: 6194/1: change definition of cpu_relax() for ARM11MPCoreWill Deacon
Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. On an ARM11MPCore processor, loads are prioritised over stores so it is possible for a store operation to be postponed if a polling loop immediately follows it. If the variable being polled indirectly depends on the outstanding store [for example, another CPU may be polling the variable that is pending modification] then there is the potential for deadlock if interrupts are disabled. This deadlock occurs in the KGDB testsuire when executing on an SMP ARM11MPCore configuration. This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 cores, forcing a flushing of the write buffer on SMP systems before the next load takes place. If the Kernel is not compiled for SMP support, this will expand to a barrier() as before. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas
When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas
When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance ↵Catalin Marinas
workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMPCatalin Marinas
A recent patch for DMA cache maintenance on ARM11MPCore added a write for ownership trick to the v6_dma_inv_range() function. Such operation destroys data already present in the buffer. However, this function is used with with dma_sync_single_for_device() which is supposed to preserve the existing data transfered into the buffer. This patch adds a combination of read/write for ownership to preserve the original data. Reported-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU buildsCatalin Marinas
This macro is not defined when !CONFIG_MMU so this patch moves the CONSISTENT_* definitions to the CONFIG_MMU section. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-07-01ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPIDaniel Mack
arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init': mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2010-06-30x86, Calgary: Limit the max PHB number to 256Darrick J. Wong
The x3950 family can have as many as 256 PCI buses in a single system, so change the limits to the maximum. Since there can only be 256 PCI buses in one domain, we no longer need the BUG_ON check. Signed-off-by: Darrick J. Wong <djwong@us.ibm.com> LKML-Reference: <20100701004519.GQ15515@tux1.beaverton.ibm.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2010-06-30Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP: hwmod: Fix the missing braces OMAP4: clock: Fix multi-omap boot with reset un-used clocks OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg omap: GPIO: fix auto-disable of debounce clock omap: DMTIMER: Ack pending interrupt always when stopping a timer omap: Stalker board: switch over to gpio_set_debounce omap: fix build failure due to missing include dma-mapping.h omap iommu: Fix Memory leak
2010-06-30[IA64] Fix spinaphore down_spin()Tony Luck
Typo in down_spin() meant it only read the low 32 bits of the "serve" value, instead of the full 64 bits. This results in the system hanging when the values in ticket/serve get larger than 32-bits. A big enough system running the right test can hit this in a just a few hours. Broken since 883a3acf5b0d4782ac35981227a0d094e8b44850 [IA64] Re-implement spinaphores using ticket lock concepts Reported via IRC by Bjorn Helgaas Signed-off-by: Tony Luck <tony.luck@intel.com>
2010-06-30x86: Send a SIGTRAP for user icebp trapsFrederic Weisbecker
Before we had a generic breakpoint layer, x86 used to send a sigtrap for any debug event that happened in userspace, except if it was caused by lazy dr7 switches. Currently we only send such signal for single step or breakpoint events. However, there are three other kind of debug exceptions: - debug register access detected: trigger an exception if the next instruction touches the debug registers. We don't use it. - task switch, but we don't use tss. - icebp/int01 trap. This instruction (0xf1) is undocumented and generates an int 1 exception. Unlike single step through TF flag, it doesn't set the single step origin of the exception in dr6. icebp then used to be reported in userspace using trap signals but this have been incidentally broken with the new breakpoint code. Reenable this. Since this is the only debug event that doesn't set anything in dr6, this is all we have to check. This fixes a regression in Wine where World Of Warcraft got broken as it uses this for software protection checks purposes. And probably other apps do. Reported-and-tested-by: Alexandre Julliard <julliard@winehq.org> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Prasad <prasad@linux.vnet.ibm.com> Cc: 2.6.33.x 2.6.34.x <stable@kernel.org>
2010-06-29um: os-linux/mem.c needs sys/stat.hLiu Aleaxander
The os-linux/mem.c file calls fchmod function, which is declared in sys/stat.h header file, so include it. Fixes build breakage under FC13. Signed-off-by: Liu Aleaxander <Aleaxander@gmail.com> Acked-by: Boaz Harrosh <bharrosh@panasas.com> Cc: Jeff Dike <jdike@addtoit.com> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-06-28Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: tracing: Fix undeclared ENOSYS in include/linux/tracepoint.h perf record: prevent kill(0, SIGTERM); perf session: Remove threads from tree on PERF_RECORD_EXIT perf/tracing: Fix regression of perf losing kprobe events perf_events: Fix Intel Westmere event constraints perf record: Don't call newt functions when not initialized
2010-06-28Merge branch 'x86-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, Calgary: Increase max PHB number x86: Fix rebooting on Dell Precision WorkStation T7400 x86: Fix vsyscall on gcc 4.5 with -Os x86, pat: Proper init of memtype subtree_max_end um, hweight: Fix UML boot crash due to x86 optimized hweight x86, setup: Set ax register in boot vga query percpu, x86: Avoid warnings of unused variables in per cpu x86, irq: Rename gsi_end gsi_top, and fix off by one errors x86: use __ASSEMBLY__ rather than __ASSEMBLER__
2010-06-28Merge branch 'for_2.6.35rc' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren
omap-fixes-for-linus
2010-06-28arm: update gfp/slab.h includesTejun Heo
Implicit slab.h inclusion via percpu.h is about to go away. Make sure gfp.h or slab.h is included as necessary. Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
2010-06-27Merge branch 'sh/for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 * 'sh/for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: clocksource: sh_cmt: Fix up bogus shift value. arch/sh/mm: Eliminate a double lock sh: Fix up IORESOURCE_PCI_FIXED usage in pcibios_fixup_device_resources(). sh: remove duplicated #include
2010-06-27Merge branch 'merge' of git://git.secretlab.ca/git/linux-2.6Linus Torvalds
* 'merge' of git://git.secretlab.ca/git/linux-2.6: powerpc/5200: fix lite5200 ethernet phy address powerpc/5200: Fix build error in sound code. powerpc/5200: fix oops during going to standby powerpc/5200: add lite5200 onboard I2C eeprom and flash maintainers: Add git trees for SPI and device tree of: Drop properties with "/" in their name
2010-06-27Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha-2.6: alpha: Fix de2104x driver failing to readout MAC address correctly alpha: Detect Super IO chip, no IDE on Avanti, enable EPP19 alpha: fix pci_mmap_resource API breakage alpha: fix __arch_hweight32 typo
2010-06-27Merge branch 'merge' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc: Fix mpic_resume on early G5 macs powerpc: rtas_flash needs to use rtas_data_buf powerpc: Unconditionally enabled irq stacks powerpc/kexec: Wait for online/possible CPUs only. powerpc: Disable CONFIG_SYSFS_DEPRECATED powerpc/boot: Remove addRamdisk.c since it is now unused powerpc: Move kdump default base address to 64MB on 64bit powerpc: Remove dead CONFIG_HIGHPTE powerpc/fsl-booke: Move loadcam_entry back to asm code to fix SMP ftrace powerpc/fsl-booke: Fix InstructionTLBError execute permission check
2010-06-25x86, Calgary: Increase max PHB numberDarrick J. Wong
Newer systems (x3950M2) can have 48 PHBs per chassis and 8 chassis, so bump the limits up and provide an explanation of the requirements for each class. Signed-off-by: Darrick J. Wong <djwong@us.ibm.com> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com> Cc: Corinna Schultz <cschultz@linux.vnet.ibm.com> Cc: <stable@kernel.org> LKML-Reference: <20100624212647.GI15515@tux1.beaverton.ibm.com> [ v2: Fixed build bug, added back PHBS_PER_CALGARY == 4 ] Signed-off-by: Ingo Molnar <mingo@elte.hu>
2010-06-23OMAP: hwmod: Fix the missing bracesBenoit Cousson
As reported by Sergei, a couple of braces were missing after the WARN removal patch. [07/22] OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed https://patchwork.kernel.org/patch/100756/ Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: fixed patch description per Anand's E-mail] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Cc: Anand Gadiyar <gadiyar@ti.com>
2010-06-21arch/sh/mm: Eliminate a double lockJulia Lawall
The function begins and ends with a read_lock. The latter is changed to a read_unlock. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @locked@ expression E1; position p; @@ read_lock(E1@p,...); @r exists@ expression x <= locked.E1; expression locked.E1; expression E2; identifier lock; position locked.p,p1,p2; @@ *lock@p1 (E1@p,...); ... when != E1 when != \(x = E2\|&x\) *lock@p2 (E1,...); // </smpl> Signed-off-by: Julia Lawall <julia@diku.dk> Acked-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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