| Age | Commit message (Expand) | Author |
|---|
| 2009-06-10 | perf_counter: More aggressive frequency adjustment | Peter Zijlstra |
| 2009-06-10 | perf_counter/x86: Fix the model number of Intel Core2 processors | Yong Wang |
| 2009-06-10 | KVM: Add VT-x machine check support | Andi Kleen |
| 2009-06-10 | KVM: use smp_send_reschedule in kvm_vcpu_kick | Marcelo Tosatti |
| 2009-06-10 | KVM: x86: paravirt skip pit-through-ioapic boot check | Marcelo Tosatti |
| 2009-06-09 | perf_counter, x86: Correct some event and umask values for Intel processors | Yong Wang |
| 2009-06-09 | x86: Detect use of extended APIC ID for AMD CPUs | Andreas Herrmann |
| 2009-06-09 | cpumask: alloc zeroed cpumask for static cpumask_var_ts | Yinghai Lu |
| 2009-06-09 | amd-iommu: remove unnecessary "AMD IOMMU: " prefix | Joerg Roedel |
| 2009-06-09 | amd-iommu: detach device explicitly before attaching it to a new domain | Joerg Roedel |
| 2009-06-09 | amd-iommu: remove BUS_NOTIFY_BOUND_DRIVER handling | Joerg Roedel |
| 2009-06-09 | Merge commit 'tip/core/iommu' into amd-iommu/fixes | Joerg Roedel |
| 2009-06-08 | perf_counter, x86: Clean up hw_cache_event ids copies | Thomas Gleixner |
| 2009-06-08 | perf_counter, x86: Implement generalized cache event types, add AMD support | Thomas Gleixner |
| 2009-06-08 | x86, UV: Fix macros for multiple coherency domains | Jack Steiner |
| 2009-06-08 | perf_counter: Clean up x86 boot messages | Ingo Molnar |
| 2009-06-08 | perf_counter, x86: Implement generalized cache event types, add Atom support | Thomas Gleixner |
| 2009-06-08 | perf_counter, x86: Implement generalized cache event types, add Core2 support | Thomas Gleixner |
| 2009-06-07 | x86, microcode: Simplify vfree() use | Figo.zhang |
| 2009-06-07 | x86: Fix non-lazy GS handling in sys_vm86() | Lubomir Rintel |
| 2009-06-07 | x86, apic: Fix dummy apic read operation together with broken MP handling | Cyrill Gorcunov |
| 2009-06-07 | x86: Add quirk for reboot stalls on a Dell Optiplex 360 | Jean Delvare |
| 2009-06-07 | x86: cpu_debug: Remove model information to reduce encoding-decoding | Jaswinder Singh Rajput |
| 2009-06-07 | Merge branch 'linus' into x86/cpu | Ingo Molnar |
| 2009-06-07 | Merge branch 'linus' into core/iommu | Ingo Molnar |
| 2009-06-06 | Merge branch 'linus' into perfcounters/core | Ingo Molnar |
| 2009-06-06 | perf_counter: Implement generalized cache event types | Ingo Molnar |
| 2009-06-06 | perf_counter: Separate out attr->type from attr->config | Ingo Molnar |
| 2009-06-06 | x86: enable GART-IOMMU only after setting up protection methods | Mark Langsdorf |
| 2009-06-05 | [CPUFREQ] powernow-k8: check space_id of _PCT registers to be FFH | Dave Jones |
| 2009-06-03 | x86, mce: fix for mce counters | Hidetoshi Seto |
| 2009-06-03 | x86, mce: support action-optional machine checks | Andi Kleen |
| 2009-06-03 | x86, mce: rename mce_notify_user to mce_notify_irq | Andi Kleen |
| 2009-06-03 | x86: fix panic with interrupts off (needed for MCE) | Andi Kleen |
| 2009-06-03 | x86, mce: export MCE severities coverage via debugfs | Huang Ying |
| 2009-06-03 | x86, mce: implement new status bits | Andi Kleen |
| 2009-06-03 | x86, mce: print header/footer only once for multiple MCEs | Andi Kleen |
| 2009-06-03 | x86, mce: default to panic timeout for machine checks | Andi Kleen |
| 2009-06-03 | x86, mce: improve mce_get_rip | Huang Ying |
| 2009-06-03 | x86, mce: make non Monarch panic message "Fatal machine check" too | Andi Kleen |
| 2009-06-03 | x86, mce: switch x86 machine check handler to Monarch election. | Andi Kleen |
| 2009-06-03 | x86, mce: implement panic synchronization | Andi Kleen |
| 2009-06-03 | x86, mce: implement bootstrapping for machine check wakeups | Andi Kleen |
| 2009-06-03 | x86, mce: check early in exception handler if panic is needed | Andi Kleen |
| 2009-06-03 | x86, mce: add table driven machine check grading | Andi Kleen |
| 2009-06-03 | x86, mce: remove TSC print heuristic | Andi Kleen |
| 2009-06-03 | x86, mce: log corrected errors when panicing | Andi Kleen |
| 2009-06-03 | x86, mce: extend struct mce user interface with more information. | Andi Kleen |
| 2009-06-03 | x86, mce: support more than 256 CPUs in struct mce | Andi Kleen |
| 2009-06-03 | x86, mce: store record length into memory struct mce anchor | Andi Kleen |
