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path: root/arch/riscv/mm
AgeCommit message (Expand)Author
2020-01-03riscv: mm: use __pa_symbol for kernel symbolsZong Li
2019-12-27riscv: export flush_icache_all to modulesOlof Johansson
2019-12-20riscv: move sifive_l2_cache.c to drivers/socChristoph Hellwig
2019-12-04Merge tag 'riscv/for-v5.5-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds
2019-11-28Merge tag 'ioremap-5.5' of git://git.infradead.org/users/hch/ioremapLinus Torvalds
2019-11-22Merge branch 'next/misc2' into for-nextPaul Walmsley
2019-11-22Merge branch 'next/nommu' into for-nextPaul Walmsley
2019-11-22Merge branch 'next/misc' into for-nextPaul Walmsley
2019-11-22RISC-V: Add address map dumperYash Shah
2019-11-17riscv: add nommu supportChristoph Hellwig
2019-11-13riscv: implement remote sfence.i using IPIsChristoph Hellwig
2019-11-12riscv: Use PMD_SIZE to replace PTE_PARENT_SIZEZong Li
2019-11-11riscv: use the generic ioremap codeChristoph Hellwig
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-10-29RISC-V: Issue a tlb page flush if possibleAtish Patra
2019-10-29RISC-V: Issue a local tlbflush if possible.Atish Patra
2019-10-29RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra
2019-10-28riscv: add missing header file includesPaul Walmsley
2019-10-28riscv: mark some code and data as file-staticPaul Walmsley
2019-10-28riscv: init: merge split string literals in preprocessor directivePaul Walmsley
2019-10-28riscv: add prototypes for assembly language functions from head.SPaul Walmsley
2019-10-23riscv: Fix undefined reference to vmemmap_populate_basepagesKefeng Wang
2019-10-01riscv: Fix memblock reservation for device tree blobAlbert Ou
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig
2019-08-30RISC-V: Implement sparsememLogan Gunthorpe
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng
2019-07-18Merge tag 'riscv/for-v5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds
2019-07-09RISC-V: Setup initial page tables in two stagesAnup Patel
2019-07-08Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds
2019-07-04riscv: remove free_initrd_memChristoph Hellwig
2019-07-04riscv: ccache: Remove unused variableYash Shah
2019-07-03riscv: Introduce huge page support for 32/64bit kernelAlexandre Ghiti
2019-07-01RISC-V: Fix memory reservation in setup_bootmem()Anup Patel
2019-06-26riscv: mm: Fix code commentShihPo Hung
2019-06-17Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds
2019-06-17riscv: mm: synchronize MMU after pte changeShihPo Hung
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner
2019-05-29signal/riscv: Remove tsk parameter from do_trapEric W. Biederman
2019-05-24treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 120Thomas Gleixner
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner
2019-05-19Merge tag 'riscv-for-linus-5.2-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds
2019-05-16riscv: fix locking violation in page fault handlerAndreas Schwab
2019-05-16RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCsYash Shah
2019-05-16riscv: move switch_mm to its own fileGary Guo
2019-05-16riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel
2019-05-14riscv: switch over to generic free_initmem()Mike Rapoport
2019-04-10RISC-V: Fix Maximum Physical Memory 2GiB option for 64bit systemsAnup Patel
2019-03-26RISC-V: Always compile mm/init.c with cmodel=medany and notraceAnup Patel