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Implements support for the OpenRISC timer which is a 28 bit cycle counter
that can be read out of a special purpose register. This counter is
used as a both a clock event and clocksource device.
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Cc: tglx@linutronix.de
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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Simple DMA implementation. Allows for allocation of coherent memory
(simply uncached) for DMA operations.
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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This patch implements minimal PTrace support. The pt_regs structure is
not exported to userspace for OpenRISC; rather, the GETREGSET mechanism
is intended to be used and the registers, as such, exported in the core
dump format which is ABI stable. This is in line with what is intended
for new architectures as of 2.6.34 and has the advantage of permitting
the layout of the registers on the kernel stack (as per pt_regs) to be
freely modified.
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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Signed-off-by: Jonas Bonn <jonas@southpole.se>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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Signed-off-by: Jonas Bonn <jonas@southpole.se>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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Signed-off-by: Jonas Bonn <jonas@southpole.se>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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The OpenRISC architecture uses the device tree infrastructure for the
platform description. This is currently limited to having a device tree
built into the kernel, but work is underway within the OpenRISC project
to define how this device tree blob should be passed into the kernel from
an external resource.
Patch contains a single example DTS file to go with the defconfig for
or1ksim.
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Cc: devicetree-discuss@lists.ozlabs.org
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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Architecture code and early setup routines for booting Linux.
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
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