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Redefine trap handler as below:
0 N/A reserved for system calls
1 SIGUSR1 user-defined signal 1
2 SIGUSR2 user-defined signal 2
3 SIGILL illegal instruction
4..29 reserved (but implemented to raise SIGILL instead of being undefined)
30 SIGTRAP KGDB
31 SIGTRAP trace/breakpoint trap
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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Remove the end address checking for flushda function. We need to flush
each address line for flushda instruction, from start to end address.
This is because flushda instruction only flush the cache if tag and line
fields are matched.
Change to use ldwio instruction (bypass cache) to load the instruction
that causing trap. Our interest is the actual instruction that executed
by the processor, this should be uncached.
Note, EA address might be an userspace cached address.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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Signed-off-by: Ley Foon Tan <lftan@altera.com>
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Follow aa0d53260596 ("ia64: Use preempt_schedule_irq") and use
preempt_schedule_irq instead of enabling/disabling interrupts and
messing around with PREEMPT_ACTIVE in the nios2 low-level preemption
code ourselves. Also get rid of the now needless re-check for
TIF_NEED_RESCHED, preempt_schedule_irq will already take care of
rescheduling.
This also fixes the following build error when building with
CONFIG_PREEMPT:
arch/nios2/kernel/built-in.o: In function `need_resched':
arch/nios2/kernel/entry.S:374: undefined reference to `PREEMPT_ACTIVE'
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Acked-by: Ley Foon Tan <lftan@altera.com>
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This patch contains the exception entry code (kernel/entry.S) and
misaligned exception.
Signed-off-by: Ley Foon Tan <lftan@altera.com>
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