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2014-01-24MIPS: Netlogic: SYS block updates of XLP9XXJayachandran C
Add the SYS block registers for XLP9XX, most of them have changed. The wakeup sequence has been updated to set the coherent mode from the main thread rather than the woken up thread. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6280/
2014-01-24MIPS: Netlogic: XLP9XX PIC updatesJayachandran C
Functions for the XLP9XX interrupt table entry format and other PIC register changes. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6279/
2014-01-24MIPS: Netlogic: update iomap.h for XLP9XXJayachandran C
Most IO block offsets have changed in XLP9XX. Update iomap.h to add the new addresses of different SoC blocks like PIC, SYS, UART etc. that are needed by the base code. On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus corresponding to the node. Update iomap code to reflect this. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6277/
2014-01-24MIPS: Netlogic: Identify XLP 9XX chipJayachandran C
Adds processor ID of XLP 9XX to asm/cpu.h. Update netlogic/xlp-hal/xlp.h to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6274/
2014-01-24MIPS: Netlogic: Add macro for node presentJayachandran C
Add macro nlm_node_present() that can be used to check if a node is present in a multi-chip configuration. This can be used even when NUMA is not enabled. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6272/
2014-01-24MIPS: Netlogic: Add topology.h for XLP familyJayachandran C
Add mach-netlogic/topology.h which contains XLP cpu number to core and node mapping. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6271/
2014-01-24MIPS: Netlogic: Add MSI support for XLPJayachandran C
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
2014-01-24MIPS: jz4740: update platform data for JZ4740 usb device controllerApelete Seketeli
The platform data already available in tree for JZ4740 USB Device Controller was previously used by an out-of-tree USB gadget driver which was not relying on the musb driver and was written by Ingenic and the Qi-Hardware community. Update platform data for JZ4740 USB device controller to be used with musb driver. Signed-off-by: Apelete Seketeli <apelete@seketeli.net> Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6265/
2014-01-24MIPS: clean up resume declarationPaul Burton
This patch cleans up the declaration of the resume function by replacing void pointers with their correct types. The irrelevant & incorrect comment preceeding the resume function is replaced by one documenting its function. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6146/
2014-01-23Merge branch 'akpm' (incoming from Andrew)Linus Torvalds
Merge second patch-bomb from Andrew Morton: - various misc bits - the rest of MM - add generic fixmap.h, use it - backlight updates - dynamic_debug updates - printk() updates - checkpatch updates - binfmt_elf - ramfs - init/ - autofs4 - drivers/rtc - nilfs - hfsplus - Documentation/ - coredump - procfs - fork - exec - kexec - kdump - partitions - rapidio - rbtree - userns - memstick - w1 - decompressors * emailed patches from Andrew Morton <akpm@linux-foundation.org>: (197 commits) lib/decompress_unlz4.c: always set an error return code on failures romfs: fix returm err while getting inode in fill_super drivers/w1/masters/w1-gpio.c: add strong pullup emulation drivers/memstick/host/rtsx_pci_ms.c: fix ms card data transfer bug userns: relax the posix_acl_valid() checks arch/sh/kernel/dwarf.c: use rbtree postorder iteration helper instead of solution using repeated rb_erase() fs-ext3-use-rbtree-postorder-iteration-helper-instead-of-opencoding-fix fs/ext3: use rbtree postorder iteration helper instead of opencoding fs/jffs2: use rbtree postorder iteration helper instead of opencoding fs/ext4: use rbtree postorder iteration helper instead of opencoding fs/ubifs: use rbtree postorder iteration helper instead of opencoding net/netfilter/ipset/ip_set_hash_netiface.c: use rbtree postorder iteration instead of opencoding rbtree/test: test rbtree_postorder_for_each_entry_safe() rbtree/test: move rb_node to the middle of the test struct rapidio: add modular rapidio core build into powerpc and mips branches partitions/efi: complete documentation of gpt kernel param purpose kdump: add /sys/kernel/vmcoreinfo ABI documentation kdump: fix exported size of vmcoreinfo note kexec: add sysctl to disable kexec_load fs/exec.c: call arch_pick_mmap_layout() only once ...
2014-01-23Merge tag 'clk-for-linus-3.14-part1' of ↵Linus Torvalds
git://git.linaro.org/people/mike.turquette/linux Pull clk framework changes from Mike Turquette: "The first half of the clk framework pull request is made up almost entirely of new platform/driver support. There are some conversions of existing drivers to the common-clock Device Tree binding, and a few non-critical fixes to the framework. Due to an entirely unnecessary cyclical dependency with the arm-soc tree this pull request is broken into two pieces. The second piece will be sent out after arm-soc sends you the pull request that merged in core support for the HiSilicon 3620 platform. That same pull request from arm-soc depends on this pull request to merge in those HiSilicon bits without causing build failures" [ Just did the ARM SoC merges, so getting ready for the second clk tree pull request - Linus ] * tag 'clk-for-linus-3.14-part1' of git://git.linaro.org/people/mike.turquette/linux: (97 commits) devicetree: bindings: Document qcom,mmcc devicetree: bindings: Document qcom,gcc clk: qcom: Add support for MSM8660's global clock controller (GCC) clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8974's global clock controller (GCC) clk: qcom: Add support for MSM8960's multimedia clock controller (MMCC) clk: qcom: Add support for MSM8960's global clock controller (GCC) clk: qcom: Add reset controller support clk: qcom: Add support for branches/gate clocks clk: qcom: Add support for root clock generators (RCGs) clk: qcom: Add support for phase locked loops (PLLs) clk: qcom: Add a regmap type clock struct clk: Add set_rate_and_parent() op reset: Silence warning in reset-controller.h clk: sirf: re-arch to make the codes support both prima2 and atlas6 clk: composite: pass mux_hw into determine_rate clk: shmobile: Fix MSTP clock array initialization clk: shmobile: Fix MSTP clock index ARM: dts: Add clock provider specific properties to max77686 node clk: max77686: Register OF clock provider ...
2014-01-23mips: use generic fixmap.hMark Salter
Signed-off-by: Mark Salter <msalter@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-01-23MIPS: include linux/types.hQais Yousef
The file uses u16 type but doesn't include its definition explicitly I was getting this error when including this header in my driver: arch/mips/include/asm/mipsregs.h:644:33: error: unknown type name ‘u16’ Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> Reviewed-by: Steven J. Hill <Steven.Hill@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6212/
2014-01-23MIPS: BCM63XX: use linux/serial_bcm63xx.hFlorian Fainelli
Update the early_printk code to include linux/serial_bcm63xx.h which provides the definitions for the UART block registers. While at it, remove the inclusion of serial_bcm63xx.h which was just there to allow smooth transition. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6203/
2014-01-23MIPS: BCM63XX: move UART register definitionsFlorian Fainelli
Move the BCM63XX UART driver definitions to include/linux/serial_bcm63xx.h such that we do not rely on the MIPS BCM63XX code to provide these for us. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6202/
2014-01-23MIPS: OCTEON: Supply OCTEON+ USB nodes in internal device trees.David Daney
This will be needed by the next patch to use said nodes for probing via the device tree. Signed-off-by: David Daney <david.daney@cavium.com> Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6185/
2014-01-23MIPS: Malta: mux & enable SERIRQ interruptPaul Burton
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6182/
2014-01-23MIPS: Fix build error seen in some configurationsGuenter Roeck
The following build error is seen if CONFIG_32BIT is undefined, CONFIG_64BIT is defined, and CONFIG_MIPS32_O32 is undefined. asm/syscall.h: In function 'mips_get_syscall_arg': arch/mips/include/asm/syscall.h:32:16: error: unused variable 'usp' [-Werror=unused-variable] cc1: all warnings being treated as errors Fixes: c0ff3c53d4f9 ('MIPS: Enable HAVE_ARCH_TRACEHOOK') Signed-off-by: Guenter Roeck <linux@roeck-us.net> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6160/
2014-01-22MIPS: VPE: Remove vpe_getuid and vpe_getgidEric W. Biederman
The linux build-bot recently reported a build error in arch/mips/kernel/vpe.c tree: git://git.kernel.org/pub/scm/linux/kernel/git/ebiederm/user-namespace.git for-linus head: 261000a56b6382f597bcb12000f55c9ff26a1efb commit: 261000a56b6382f597bcb12000f55c9ff26a1efb [4/4] userns: userns: Remove UIDGID_STRICT_TYPE_CHECKS config: make ARCH=mips maltaaprp_defconfig All error/warnings: arch/mips/kernel/vpe.c: In function 'vpe_open': >> arch/mips/kernel/vpe.c:1086:9: error: incompatible types when assigning to type 'unsigned int' from type 'kuid_t' >> arch/mips/kernel/vpe.c:1087:9: error: incompatible types when assigning to type 'unsigned int' from type 'kgid_t' vim +1086 arch/mips/kernel/vpe.c 863abad4 Jesper Juhl 2010-10-30 1080 return -ENOMEM; 863abad4 Jesper Juhl 2010-10-30 1081 } e01402b1 Ralf Baechle 2005-07-14 1082 v->plen = P_SIZE; e01402b1 Ralf Baechle 2005-07-14 1083 v->load_addr = NULL; e01402b1 Ralf Baechle 2005-07-14 1084 v->len = 0; e01402b1 Ralf Baechle 2005-07-14 1085 d76b0d9b David Howells 2008-11-14 @1086 v->uid = filp->f_cred->fsuid; d76b0d9b David Howells 2008-11-14 @1087 v->gid = filp->f_cred->fsgid; 2600990e Ralf Baechle 2006-04-05 1088 2600990e Ralf Baechle 2006-04-05 1089 v->cwd[0] = 0; 2600990e Ralf Baechle 2006-04-05 1090 ret = getcwd(v->cwd, VPE_PATH_MAX); When examining the code to see what v->uid and v->gid were used for I discovered that the only users in the kernel are vpe_getuid and vpe_getgid, and that vpe_getuid and vpe_getgid are never called. So instead of proposing a conversion to use kuid_t and kgid_t instead of unsigned int/int as I normally would let's just kill this dead code so no one has to worry about it further. Deng-Cheng Zhu said: This is a good catch. vpe_get[u|g]id was originally used by KSPD which has been removed. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Reviewed-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2014-01-22MIPS: improve checks for noncoherent DMAFelix Fietkau
Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5912/
2014-01-22MIPS: APRP: Code formatting clean-ups.Steven J. Hill
Clean-up code according to the 'checkpatch.pl' script. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6097/ Reviewed-by: John Crispin <blogic@openwrt.org>
2014-01-22MIPS: APRP: Add support for Malta CMP platform.Deng-Cheng Zhu
Malta with multi-core CM platforms can now use APRP functionality. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6096/
2014-01-22MIPS: APRP: Add RTLX API support for CMP platforms.Deng-Cheng Zhu
This patch adds RTLX API support for platforms having a CMP. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6095/ Reviewed-by: John Crispin <blogic@openwrt.org>
2014-01-22MIPS: APRP: Split RTLX support into separate files.Deng-Cheng Zhu
Split the RTLX functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6093/ Reviewed-by: John Crispin <blogic@openwrt.org>
2014-01-22MIPS: APRP: Split VPE loader into separate files.Deng-Cheng Zhu
Split the VPE functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP present. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Qais Yousef <Qais.Yousef@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6094/
2014-01-22MIPS: Add support for interAptiv coresLeonid Yegoshin
The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6163/
2014-01-22MIPS: Add processor identifiers for the interAptiv processorsLeonid Yegoshin
Add processor identifiers for UP and MT interAptiv processors. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6151/
2014-01-22MIPS: Add support for FTLBsLeonid Yegoshin
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
2014-01-22MIPS: Add function for flushing the TLB using the TLBINV instructionLeonid Yegoshin
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6136/
2014-01-22MIPS: Add support for the proAptiv coresLeonid Yegoshin
The proAptiv Multiprocessing System is a power efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The proAptiv Multiprocessing System combines a deep pipeline with multi-issue out of order execution for improved computational throughput. The proAptiv Multiprocessing System can contain one to six MIPS32r3 proAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6134/
2014-01-22MIPS: Add processor identifiers for the proAptiv processorsLeonid Yegoshin
Add processor identifiers for single core and multi-core proAptiv processors. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6133/
2014-01-22MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLBLeonid Yegoshin
For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6132/
2014-01-22MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill
MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6131/
2014-01-22MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin
New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6130/
2014-01-22MIPS: mm: Move UNIQUE_ENTRYHI macro to a header fileMarkos Chandras
The UNIQUE_ENTRYHI definition was duplicated whenever there was the need to flush the TLB entries. We move this common definition to a header file. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6129/
2014-01-22MIPS: Add missing bits for Config registersLeonid Yegoshin
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6128/
2014-01-22MIPS: BCM47XX: add cpu-feature-overrides.hHauke Mehrtens
The BCM47XX SoC code missed a cpu-feature-overrides.h header file, this patch adds it. This code supports a long line of SoCs with different features so for some features we still have to rely on the runtime detection. This was crated by checking the features of a BCM4712, BCM4704, BCM5354, BCM4716 and BCM4706 SoC and then tested on these SoCs. There are some SoCs missing but I hope they do not have any more or less features. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6289/
2014-01-22MIPS: BCM47XX: only print SoC name in system type in cpuinfoHauke Mehrtens
Recently the output of "system type" in /proc/cpuinfo was changed to Broadcom BCM4730 (Some sample board), but it is better to just print the SoC name in the "system type" entry. The board name will be added in the machine entry later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5865/
2014-01-22MIPS: cpu-type: guard BMIPS variants with SYS_HAS_CPU_BMIPS*Jonas Gorski
BMIPS32 and BMIPS3300 also need to be available for MIPS32R1, as bcm47xx might not select BMIPS. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6245/
2014-01-22MIPS: BMIPS: add a smp ops registration helperJonas Gorski
Add a helper similar to the generic register_XXX_smp_ops() for bmips. Register SMP UP ops in case of BMIPS32/3300. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6248/
2014-01-22MIPS: BMIPS: change compile time checks to runtime checksJonas Gorski
Allow building for all bmips cpus at the same time by changing ifdefs to checks for the cpu type, or adding appropriate checks to the assembly. Since BMIPS43XX and BMIPS5000 require different IPI implementations, split the SMP ops into one for each, so the runtime overhead is only at registration time for them. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6241/
2014-01-22MIPS: allow asm/cpu.h to be included from assemblyJonas Gorski
Add guards around the enum to allow including cpu.h from assembly. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6238/
2014-01-22MIPS: BCM63XX: add HSSPI platform device and register itJonas Gorski
Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6180/
2014-01-22MIPS: BCM63XX: add HSSPI IRQ and register offsetsJonas Gorski
Signed-off-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6179/
2014-01-20Merge branch 'core-locking-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull core locking changes from Ingo Molnar: - futex performance increases: larger hashes, smarter wakeups - mutex debugging improvements - lots of SMP ordering documentation updates - introduce the smp_load_acquire(), smp_store_release() primitives. (There are WIP patches that make use of them - not yet merged) - lockdep micro-optimizations - lockdep improvement: better cover IRQ contexts - liblockdep at last. We'll continue to monitor how useful this is * 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) futexes: Fix futex_hashsize initialization arch: Re-sort some Kbuild files to hopefully help avoid some conflicts futexes: Avoid taking the hb->lock if there's nothing to wake up futexes: Document multiprocessor ordering guarantees futexes: Increase hash table size for better performance futexes: Clean up various details arch: Introduce smp_load_acquire(), smp_store_release() arch: Clean up asm/barrier.h implementations using asm-generic/barrier.h arch: Move smp_mb__{before,after}_atomic_{inc,dec}.h into asm/atomic.h locking/doc: Rename LOCK/UNLOCK to ACQUIRE/RELEASE mutexes: Give more informative mutex warning in the !lock->owner case powerpc: Full barrier for smp_mb__after_unlock_lock() rcu: Apply smp_mb__after_unlock_lock() to preserve grace periods Documentation/memory-barriers.txt: Downgrade UNLOCK+BLOCK locking: Add an smp_mb__after_unlock_lock() for UNLOCK+BLOCK barrier Documentation/memory-barriers.txt: Document ACCESS_ONCE() Documentation/memory-barriers.txt: Prohibit speculative writes Documentation/memory-barriers.txt: Add long atomic examples to memory-barriers.txt Documentation/memory-barriers.txt: Add needed ACCESS_ONCE() calls to memory-barriers.txt Revert "smp/cpumask: Make CONFIG_CPUMASK_OFFSTACK=y usable without debug dependency" ...
2014-01-18Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller
Conflicts: drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c net/ipv4/tcp_metrics.c Overlapping changes between the "don't create two tcp metrics objects with the same key" race fix in net and the addition of the destination address in the lookup key in net-next. Minor overlapping changes in bnx2x driver. Signed-off-by: David S. Miller <davem@davemloft.net>
2014-01-15MIPS: fix blast_icache32 on loongson2Aaro Koskinen
Commit 14bd8c082016 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips") failed to add Loongson2 specific blast_icache32 functions. Fix that. The patch fixes the following crash seen with 3.13-rc1: Reserved instruction in kernel code[#1]: [...] Call Trace: blast_icache32_page+0x8/0xb0 r4k_flush_cache_page+0x19c/0x200 do_wp_page.isra.97+0x47c/0xe08 handle_mm_fault+0x938/0x1118 __do_page_fault+0x140/0x540 resume_userspace_check+0x0/0x10 Code: 00200825 64834000 00200825 <bc900000> bc900020 bc900040 bc900060 bc900080 bc9000a0 Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: John Crispin <blogic@openwrt.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-01-15MIPS: fix case mismatch in local_r4k_flush_icache_range()Huacai Chen
Currently, Loongson-2 call protected_blast_icache_range() and others call protected_loongson23_blast_icache_range(), but I think the correct behavior should be the opposite. BTW, Loongson-3's cache-ops is compatible with MIPS64, but not compatible with Loongson-2. So, rename xxx_loongson23_yyy things to xxx_loongson2_yyy. The patch fixes early boot hang with 3.13-rc1, introduced in commit 14bd8c082016 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips"). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: John Crispin <blogic@openwrt.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-01-13MIPS: Support for 64-bit FP with O32 binariesPaul Burton
CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-13MIPS: Remove unused {en,dis}able_fpu macrosPaul Burton
These macros are not used anywhere in the kernel. Remove them. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6111/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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