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2013-06-25ARM: sti: Add STiH416 SOC supportSrinivas Kandagatla
The STiH416 is advanced HD AVC processor with 3D graphics acceleration and 1.2-GHz ARM Cortex-A9 SMP CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-25ARM: sti: Add STiH415 SOC supportSrinivas Kandagatla
The STiH415 is the next generation of HD, AVC set-top box processors for satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9 1.0 GHz, dual-core CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-25ARM: tegra: fix section mismatch in tegra_pmc_parse_dtStephen Warren
tegra_pmc_parse_dt() references __initconst data. Fix it to be __init. This matches its only usage; a call from tegra_pmc_init() which is already __init. This fixes: WARNING: vmlinux.o(.text.unlikely+0x580): Section mismatch in reference from the function tegra_pmc_parse_dt() to the (unknown reference) .init.rodata:(unknown) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-25Merge tag 'fixes-non-3.11-2' of git://git.infradead.org/users/jcooper/linux ↵Olof Johansson
into next/fixes-non-critical From Jason Cooper: - mv78260: catch missing fix for mvneta register length * tag 'fixes-non-3.11-2' of git://git.infradead.org/users/jcooper/linux: ARM: mvebu: fix length of ethernet registers in mv78260 dtsi Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-25Merge tag 'soc-exynos5420-2' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/late From Kukjin Kim, this adds pinctrl support for Exynos 5420. * tag 'soc-exynos5420-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: pinctrl: exynos: add exynos5420 SoC specific data ARM: dts: add pinctrl support to EXYNOS5420 Signed-off-by: Olof Johansson <olof@lixom.net>
2013-06-25arm: orion: Use irq_get_trigger_type() to get IRQ flagsJavier Martinez Canillas
Use irq_get_trigger_type() to get the IRQ trigger type flags instead calling irqd_get_trigger_type(irq_get_irq_data(irq)) Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Grant Likely <grant.likely@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1371228049-27080-6-git-send-email-javier.martinez@collabora.co.uk Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-06-24Merge 3.10-rc7 into usb-nextGreg Kroah-Hartman
We want the USB fixes and other good stuff in this branch as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-24Merge 3.10-rc7 into driver-core-nextGreg Kroah-Hartman
We want the firmware merge fixes, and other bits, in here now. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-06-24ARM: msm: Migrate to common clock frameworkStephen Boyd
Move the existing clock code in mach-msm to the common clock framework. We lose our capability to set the rate of and enable a clock through debugfs. This is ok though because the debugfs features are mainly used for testing and development of new clock code. To maintain compatibility with the original MSM clock code we make a wrapper for clk_reset() that calls the struct msm_clk specific reset function. This is necessary for the usb and sdcc devices on MSM until a better suited API is made available. Cc: Saravana Kannan <skannan@codeaurora.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-24ARM: msm: Make proc_comm clock control into a platform driverStephen Boyd
To move closer to the generic struct clock framework move the proc_comm based clock code to a platform driver. The data describing the struct clks still live in the devices-$ARCH file, but the clock initialization is done at driver binding time. Cc: Saravana Kannan <skannan@codeaurora.org> Reviewed-by: Pankaj Jangra <jangra.pankaj9@gmail.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-24ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driverStephen Boyd
In the near future we'll be moving clock-pcom to a platform driver, in which case these two users of clk_get() in mach-msm need to be updated. Have board-trout-panel.c make the proc_comm call directly so that we don't have to port this board specific code to the driver right now and reorder the initcall order of dma.c so that it initializes after the clock driver probes but before any drivers use dma APIs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-24ARM: msm: Remove clock-7x30.h include fileStephen Boyd
This file is not used outside of the two users in the clock-7x30 array. Those two clocks are virtual "source" clocks that don't really need to exist outside of the clock driver. Let's remove them from the array, since they're not doing anything anyway, and then remove the clock-7x30.h include file along with it. Cc: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-24ARM: msm: Remove custom clk_set_{max,min}_rate() APIStephen Boyd
There are no users of this API anymore so let's just remove it. If a need arises in the future we can extend the common clock API to handle it. Acked-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-24ARM: msm: Remove custom clk_set_flags() APIStephen Boyd
Nobody is using this API upstream and it's just contributing cruft. Remove it so the MSM clock API is closer to the generic struct clock API. Acked-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
2013-06-24Merge tag 'davinci-for-v3.11/soc-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc From Sekhar Nori: DaVinci SoC updates for v3.11 - part 2 This pull request adds DT and runtime PM to EDMA ARM private API so it can be used on DT enabled DaVinci and OMAP platforms. Also adds DMA channel crossbar mapping support to be used by DT-enabled platforms which use it. * tag 'davinci-for-v3.11/soc-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding ARM: edma: Convert to devm_* api Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-24ARM: 7770/1: remove residual ARMv2 support from decompressorMarc Zyngier
arm26 support in Linux is long gone, yet it left an interresting, fossilized trace in the decompressor. Remove it so people won't get confused about what teqp is actually doing here... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7769/1: Cortex-A15: fix erratum 798181 implementationMarc Zyngier
Looking into the active_asids array is not enough, as we also need to look into the reserved_asids array (they both represent processes that are currently running). Also, not holding the ASID allocator lock is racy, as another CPU could schedule that process and trigger a rollover, making the erratum workaround miss an IPI. Exposing this outside of context.c is a little ugly on the side, so let's define a new entry point that the erratum workaround can call to obtain the cpumask. Cc: <stable@vger.kernel.org> # 3.9 Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7768/1: prevent risks of out-of-bound access in ASID allocatorMarc Zyngier
On a CPU that never ran anything, both the active and reserved ASID fields are set to zero. In this case the ASID_TO_IDX() macro will return -1, which is not a very useful value to index a bitmap. Instead of trying to offset the ASID so that ASID #1 is actually bit 0 in the asid_map bitmap, just always ignore bit 0 and start the search from bit 1. This makes the code a bit more readable, and without risk of OoB access. Cc: <stable@vger.kernel.org> # 3.9 Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7767/1: let the ASID allocator handle suspended animationMarc Zyngier
When a CPU is running a process, the ASID for that process is held in a per-CPU variable (the "active ASIDs" array). When the ASID allocator handles a rollover, it copies the active ASIDs into a "reserved ASIDs" array to ensure that a process currently running on another CPU will continue to run unaffected. The active array is zero-ed to indicate that a rollover occurred. Because of this mechanism, a reserved ASID is only remembered for a single rollover. A subsequent rollover will completely refill the reserved ASIDs array. In a severely oversubscribed environment where a CPU can be prevented from running for extended periods of time (think virtual machines), the above has a horrible side effect: [P{a} denotes process P running with ASID a] CPU-0 CPU-1 A{x} [active = <x 0>] [suspended] runs B{y} [active = <x y>] [rollover: active = <0 0> reserved = <x y>] runs B{y} [active = <0 y> reserved = <x y>] [rollover: active = <0 0> reserved = <0 y>] runs C{x} [active = <0 x>] [resumes] runs A{x} At that stage, both A and C have the same ASID, with deadly consequences. The fix is to preserve reserved ASIDs across rollovers if the CPU doesn't have an active ASID when the rollover occurs. Cc: <stable@vger.kernel.org> # 3.9 Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Carinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7766/1: versatile: don't mark pen as __INITMark Rutland
When booting fewer cores than are physically present on a versatile platform (e.g. when passing maxcpus=N on the command line), some secondary cores may remain in the holding pen, which is marked __INIT, as each CPU's gic cpumask is initialised to 0xff, and thus an IPI to any CPU will wake up *all* secondaries. This behaviour is crucial to the GIC cpumask self-discovery. Late in the boot process, the memory comprising the holding pen will be released to the kernel for more general use, and may be overwritten with arbitrary data, which can cause the held secondaries to start behaving unpredictably. This can lead to all manner of odd behaviour from the kernel. As preventing cpus from entering the pen would require invasive changes to the GIC driver and to existing dts used in the wild, we instead remove the __INIT marker from the pen, keeping it around and leaving the unused secondary CPUs dormant. Link: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/175039.html Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: keystone: Move CPU bringup code to dedicated asm fileSantosh Shilimkar
Because of inline asm usage in platsmp.c, smc instruction creates build failure for ARM V6+V7 build where as using instruction encoding for smc breaks the thumb2 build. So move the code snippet to separate asm file and mark it with 'armv7-a$(plus_sec)' to avoid any build issues. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-24ARM: 7765/1: perf: Record the user-mode PC in the call chain.Jed Davis
With this change, we no longer lose the innermost entry in the user-mode part of the call chain. See also the x86 port, which includes the ip. It's possible to partially work around this problem by post-processing the data to use the PERF_SAMPLE_IP value, but this works only if the CPU wasn't in the kernel when the sample was taken. Cc: <stable@vger.kernel.org> Signed-off-by: Jed Davis <jld@mozilla.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7735/2: Preserve the user r/w register TPIDRURW on context switch and forkAndré Hentschel
Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to prevent it from being used as a covert channel between two tasks. There are more and more applications coming to Windows RT, Wine could support them, but mostly they expect to have the thread environment block (TEB) in TPIDRURW. This patch preserves that register per thread instead of clearing it. Unlike the TPIDRURO, which is already switched, the TPIDRURW can be updated from userspace so needs careful treatment in the case that we modify TPIDRURW and call fork(). To avoid this we must always read TPIDRURW in copy_thread. Signed-off-by: André Hentschel <nerv@dawncrow.de> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: multiplatform: always pick one CPU typeArnd Bergmann
With the new default platform code, we can always boot using DT without requiring a board file, but we cannot build a kernel unless we select at least one CPU core, which breaks some "randconfig" builds. This adapts the ARCH_MULTI_V4T and ARCH_MULTI_V5 options so we always default to a common CPU core if no platform was enabled that picks something else. The default we pick for ARMv4T is ARM920T, while for ARMv5 we pick ARM926T. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-24ARM: imx: select syscon for IMX6SLArnd Bergmann
This is required for building a kernel that enables only IMX6SL but not IMX6Q, which would get a build error when syscon is not available. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-24ARM: keystone: select ARM_ERRATA_798181 only for SMPArnd Bergmann
Selecting this symbol causes a build warning without SMP: warning: (ARCH_KEYSTONE) selects ARM_ERRATA_798181 which has unmet direct dependencies (CPU_V7 && SMP) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2013-06-24ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1Arnd Bergmann
This is required for building a kernel that enables only scb9328 and would not get the i.MX1 specific files otherwise. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Sascha Hauer <kernel@pengutronix.de>
2013-06-24ARM: OMAP2+: AM43x: resolve SMP related build errorMohammed, Afzal
If AM43x and SMP is selected, OMAP4 & OMAP5 deselected, build error as follows, arch/arm/mach-omap2/built-in.o: In function `scu_gp_set': arch/arm/mach-omap2/sleep44xx.S:131: undefined reference to `omap4_get_scu_base' arch/arm/mach-omap2/sleep44xx.S:132: undefined reference to `scu_power_mode' arch/arm/mach-omap2/built-in.o: In function `scu_gp_clear': arch/arm/mach-omap2/sleep44xx.S:227: undefined reference to `omap4_get_scu_base' arch/arm/mach-omap2/sleep44xx.S:229: undefined reference to `scu_power_mode' Resolve it by building sleep44xx.S only for OMAP4 & OMAP5. Signed-off-by: Afzal Mohammed <afzal@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-24ARM: mxs: don't select HAVE_PWMArnd Bergmann
The HAVE_PWM symbol is only for legacy platforms that provide the PWM API without using the generic framework. MXS actually uses that framework, and selecting the symbol anyway might cause build errors like drivers/built-in.o: In function `pwm_beeper_resume': :(.text+0x1f4fc0): undefined reference to `pwm_config' :(.text+0x1f4fc8): undefined reference to `pwm_enable' drivers/built-in.o: In function `pwm_beeper_suspend': :(.text+0x1f4ffc): undefined reference to `pwm_disable' when CONFIG_PWM is disabled. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Shawn Guo <shawn.guo@linaro.org>
2013-06-24ARM: mxs: stub out mxs_pm_init for !CONFIG_PMArnd Bergmann
When building a kernel without CONFIG_PM, we get a link error from referencing mxs_pm_init in the machine descriptor. This defines a macro to NULL for that case. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Shawn Guo <shawn.guo@linaro.org>
2013-06-24ARM: 7773/1: PJ4B: Add support for errata 4742Gregory CLEMENT
This commit fixes the regression on Armada 370 (the kernal hang during boot) introduced by the commit: "ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead". When coming out of either a Wait for Interrupt (WFI) or a Wait for Event (WFE) IDLE states, a specific timing sensitivity exists between the retiring WFI/WFE instructions and the newly issued subsequent instructions. This sensitivity can result in a CPU hang scenario. The workaround is to insert either a Data Synchronization Barrier (DSB) or Data Memory Barrier (DMB) command immediately after the WFI/WFE instruction. This commit was based on the work of Lior Amsalem, but heavily modified to apply the errata fix dynamically according to the processor type thanks to the suggestions of Russell King and Nicolas Pitre. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Tested-by: Willy Tarreau <w@1wt.eu> Cc: <stable@vger.kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7772/1: Fix missing flush_kernel_dcache_page() for noMMUSimon Baatz
Commit 1bc3974 (ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_page) moved the implementation of flush_kernel_dcache_page() into mm/flush.c but did not implement it on noMMU ARM. Signed-off-by: Simon Baatz <gmbnomis@gmail.com> Acked-by: Kevin Hilman <khilman@linaro.org> Cc: <stable@vger.kernel.org> # 3.2+: 1bc3974: ARM: 7755/1 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7763/1: kernel: fix __cpu_logical_map default initializationLorenzo Pieralisi
The __cpu_logical_map array is statically initialized to 0, which is a valid MPIDR value. To prevent issues with the current implementation, this patch defines an MPIDR_INVALID value, and statically initializes the __cpu_logical_map[] array to it. Entries in the arm_dt_init_cpu_maps() tmp_map array used to stash DT reg properties while parsing DT are initialized with the MPIDR_INVALID value as well for consistency. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7762/1: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodesLorenzo Pieralisi
The introduction of the cpu-map topology node in the cpus node implies that cpus node might have children that are not cpu nodes. The DT parsing code needs updating otherwise it would check for cpu nodes properties in nodes that are not required to contain them, resulting in warnings that have no bearing on bindings defined in the dts source file. Cc: <stable@vger.kernel.org> [3.8+] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24ARM: 7760/1: cpu_fa526_do_idle: remove WFIJonas Jensen
As it was already suggested by Russell King and Arnd Bergmann: https://lkml.org/lkml/2013/5/16/133 moxart and gemini seem to be the only platforms using CPU_FA526, and instead of pointing arm_pm_idle to an empty function from platform code, it makes sense to remove WFI code from the processor specific idle function. Applies to arm-soc/for-next (and 3.10-rc1). Changes since v1: 1. remove WFI but make sure cpu_fa526_do_idle do not fall through to cpu_fa526_dcache_clean_area Note: moxart boots and prints to UART without this patch, but input is broken. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-06-24dmaengine: edma: enable build for AM33XXMatt Porter
Enable TI EDMA option on OMAP and TI_PRIV_EDMA Signed-off-by: Matt Porter <mporter@ti.com> Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2013-06-24ARM: edma: Add EDMA crossbar event mux supportMatt Porter
EDMA supports a cross bar which provides ability to mux additional events into physical channels present in the channel controller. This is required when the number of events present in the system are more than number of available physical channels. Changes by Joel: * Split EDMA xbar support out of original EDMA DT parsing patch to keep it easier for review. * Rewrite shift and offset calculation. Suggested-by: Sekhar Nori <nsekhar@ti.com> Suggested by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> [nsekhar@ti.com: fix checkpatch errors and a minor coding improvement] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2013-06-24ARM: edma: Add DT and runtime PM support to the private EDMA APIMatt Porter
Adds support for parsing the TI EDMA DT data into the required EDMA private API platform data. Enables runtime PM support to initialize the EDMA hwmod. Enables build on OMAP. Changes by Joel: * Setup default one-to-one mapping for queue_priority and queue_tc mapping as discussed in [1]. * Split out xbar stuff to separate patch. [1] * Dropped unused DT helper to convert to array * Fixed dangling pointer issue with Sekhar's changes [1] https://patchwork.kernel.org/patch/2226761/ Signed-off-by: Matt Porter <mporter@ti.com> [nsekhar@ti.com: fix checkpatch errors, build breakages. Introduce edma_setup_info_from_dt() as part of that effort] Signed-off-by: Joel A Fernandes <joelagnel@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2013-06-23ARM: mvebu: fix length of ethernet registers in mv78260 dtsiEzequiel Garcia
The length of the registers area for the Marvell 370/XP Ethernet controller was incorrect in the .dtsi: 0x2500, while it should have been 0x4000. This problem wasn't noticed because there used to be a static mapping for all the MMIO register region set up by ->map_io(). The register length was fixed in all the other device tree files, except from the armada-xp-mv78260.dtsi, in the following commit: commit cf8088c5cac6ce20d914b9131533844b9291a054 Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue May 21 12:33:27 2013 +0200 arm: mvebu: fix length of Ethernet registers area in .dtsi This commit fixes a kernel panic in mvneta_probe(), when the kernel tries to access the unmapped registers: [ 163.639092] mvneta d0070000.ethernet eth0: mac: 6e:3c:4f:87:17:2e [ 163.646962] mvneta d0074000.ethernet eth1: mac: 6a:04:4e:6f:f5:ef [ 163.654853] mvneta d0030000.ethernet eth2: mac: 2a:99:19:19:fc:4c [ 163.661258] Unable to handle kernel paging request at virtual address f011bcf0 [ 163.668523] pgd = c0004000 [ 163.671237] [f011bcf0] *pgd=2f006811, *pte=00000000, *ppte=00000000 [ 163.677565] Internal error: Oops: 807 [#1] SMP ARM [ 163.682370] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc6-01850-gba0682e #11 [ 163.690046] task: ef04c000 ti: ef03e000 task.ti: ef03e000 [ 163.695467] PC is at mvneta_probe+0x34c/0xabc [...] Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-06-22Merge tag 'fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Arnd Bergmann: "These are two fixes that came in this week, one for a regression we introduced in 3.10 in the GIC interrupt code, and the other one fixes a typo in newly introduced code" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: irqchip: gic: call gic_cpu_init() as well in CPU_STARTING_FROZEN case ARM: dts: Correct the base address of pinctrl_3 on Exynos5250
2013-06-21arm: Add Initial TI-Nspire supportDaniel Tang
This patch adds support for the TI-Nspire platform. Changes between v1 and v2: * Added GENERIC_IRQ_CHIP to platform Kconfig Signed-off-by: Daniel Tang <dt.tangr@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-21arm: Add device trees for TI-Nspire hardwareDaniel Tang
This patch adds device trees for describing the TI-Nspire hardware. Changes between v1 and v2: * Change "keymap" binding to the standard "linux,keymap" binding. Signed-off-by: Daniel Tang <dt.tangr@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-21Merge tag 'regmap-3.11-2' of git://git.infradead.org/users/jcooper/linux ↵Arnd Bergmann
into next/soc From Jason Cooper: mvebu register map changes for v3.11 (round 2) This series removes the hardcoded register base address for mvebu. For round 2: - multiplatform - fix booting on anything other than mvebu Depends (none new for round 2): - mvebu/fixes-non-critical (up to tags/fixes-non-3.11-1) - mvebu/cleanup (up to tags/cleanup-3.11-3) * tag 'regmap-3.11-2' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: fix coherency_late_init() for multiplatform Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-21Merge tag 'dt-3.11-6' of git://git.infradead.org/users/jcooper/linux into ↵Arnd Bergmann
next/dt From Jason Cooper: mvebu dt changes for v3.11 (round 6) - mvebu - mini-PCIe connectors on Armada 370 RD - kirkwood - correct internal register ranges translation * tag 'dt-3.11-6' of git://git.infradead.org/users/jcooper/linux: ARM: Kirkwood: Fix the internal register ranges translation arm: mvebu: enable mini-PCIe connectors on Armada 370 RD Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-21ARM: Kirkwood: Fix the internal register ranges translationEzequiel Garcia
Although the internal register window size is 1 MiB, the previous ranges translation for the internal register space had a size of 0x4000000. This was done to allow the crypto and nand node to access the corresponding 'sram' and 'nand' decoding windows. In order to describe the hardware more accurately, we declare the real 1 MiB internal register space in the ranges, and add a translation entry for the nand node to access the 'nand' window. This commit will make future improvements on the MBus DT binding easier. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-06-21ARM: at91: cpuidle: Fix target_residencyDaniel Lezcano
The following commit: commit 7e348b9012522fa0efd854d20d210d5e57fcedd1 Author: Robert Lee <rob.lee@linaro.org> Date: Tue Mar 20 15:22:43 2012 -0500 ARM: at91: Consolidate time keeping and irq enable Enable core cpuidle timekeeping and irq enabling and remove that handling from this code. introduced an additional zero to the state1 (suspend) target residency. With a periodic tick, the cpu never enters the state1 with both 10000 and 100000. With a tickless system, it enters to state1 much more often with the initial value, roughly x7 more. Fix it by setting the value to 10ms again. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> [nicola.ferre@atmel.com: add precisions given by Daniel to commit message] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-06-21ARM: at91: fix at91_extern_irq usage for non-dt boardsJean-Christophe PLAGNIOL-VILLARD
Since 4b68520dc0ec96153bc0d87bca5ffba508edfcf ARM: at91: add AIC5 support we allocate the at91_extern_irq. This patch makes it static and stores the non-dt extern irq in the soc structure. It is then possible to use a at91_get_extern_irq() function to get the value for outside of the irq driver. It is useful for passing its value to at91_aic_init(). Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com> [nicolas.ferre@atmel.com: rework commit message] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-06-21Merge tag 'zynq-defconfig-for-3.11' of git://git.xilinx.com/linux-xlnx into ↵Arnd Bergmann
next/boards From Michal Simek: arm: Xilinx Zynq defconfig changes for v3.11 Enable zynq uartps driver and initrd in defconfig. * tag 'zynq-defconfig-for-3.11' of git://git.xilinx.com/linux-xlnx: arm: multi_v7_defconfig: Enable initrd/initramfs support arm: multi_v7_defconfig: Enable Zynq UART driver Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-21Merge branch 'armsoc/for-3.11/cleanups' of ↵Arnd Bergmann
git://github.com/broadcom/bcm11351 into next/cleanup From Christian Daudt: * 'armsoc/for-3.11/cleanups' of git://github.com/broadcom/bcm11351: ARM: bcm281xx: Remove init_irq declaration in machine description Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-21Merge branch 'armsoc/for-3.11/dt' of git://github.com/broadcom/bcm11351 into ↵Arnd Bergmann
next/dt From Christian Daudt: * 'armsoc/for-3.11/dt' of git://github.com/broadcom/bcm11351: ARM: dts: bcm281xx: change comment to C89 style ARM: mmc: bcm281xx SDHCI driver (dt mods) ARM: dts: bcm281xx: use existing defines for irqs ARM: dts: bcm281xx: use #include for device tree files Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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