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Age	Commit message (Collapse)	Author
2019-10-10	arm64: dts: rockchip: add cr50 tpm to rk3399-gru scarlet and bob	Heiko Stuebner
	Scarlet and Bob use the Google-developed cr50 chip to do things like TPM and closed-case-debugging. Add the nodes describing the cr50 and its spi-connection. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20180822120925.12388-1-heiko@sntech.de
2019-04-11	arm64: dts: rockchip: bulk convert gpios to their constant counterparts	Heiko Stuebner
	Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins =/bcheck b # to end of script :append-next-line N :check /^[^;]$/bappend-next-line s/<RK_GPIO$[0-9]$ /<\1 /g s/<$[^ ][^ ]* $0 /<\1RK_PA0 /g s/<$[^ ][^ ] $1 /<\1RK_PA1 /g s/<$[^ ][^ ] $2 /<\1RK_PA2 /g s/<$[^ ][^ ] $3 /<\1RK_PA3 /g s/<$[^ ][^ ] $4 /<\1RK_PA4 /g s/<$[^ ][^ ] $5 /<\1RK_PA5 /g s/<$[^ ][^ ] $6 /<\1RK_PA6 /g s/<$[^ ][^ ] $7 /<\1RK_PA7 /g s/<$[^ ][^ ] $8 /<\1RK_PB0 /g s/<$[^ ][^ ] $9 /<\1RK_PB1 /g s/<$[^ ][^ ] $10 /<\1RK_PB2 /g s/<$[^ ][^ ] $11 /<\1RK_PB3 /g s/<$[^ ][^ ] $12 /<\1RK_PB4 /g s/<$[^ ][^ ] $13 /<\1RK_PB5 /g s/<$[^ ][^ ] $14 /<\1RK_PB6 /g s/<$[^ ][^ ] $15 /<\1RK_PB7 /g s/<$[^ ][^ ] $16 /<\1RK_PC0 /g s/<$[^ ][^ ] $17 /<\1RK_PC1 /g s/<$[^ ][^ ] $18 /<\1RK_PC2 /g s/<$[^ ][^ ] $19 /<\1RK_PC3 /g s/<$[^ ][^ ] $20 /<\1RK_PC4 /g s/<$[^ ][^ ] $21 /<\1RK_PC5 /g s/<$[^ ][^ ] $22 /<\1RK_PC6 /g s/<$[^ ][^ ] $23 /<\1RK_PC7 /g s/<$[^ ][^ ] $24 /<\1RK_PD0 /g s/<$[^ ][^ ] $25 /<\1RK_PD1 /g s/<$[^ ][^ ] $26 /<\1RK_PD2 /g s/<$[^ ][^ ] $27 /<\1RK_PD3 /g s/<$[^ ][^ ] $28 /<\1RK_PD4 /g s/<$[^ ][^ ] $29 /<\1RK_PD5 /g s/<$[^ ][^ ] $30 /<\1RK_PD6 /g s/<$[^ ][^ ] $31 /<\1RK_PD7 /g s/<$[^ ][^ ] [^ ][^ ] $0 /<\1RK_FUNC_GPIO /g s/<$[^ ][^ ] [^ ][^ ] *$RK_FUNC_$[1-9]$ /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Acked-by: Robin Murphy <robin.murphy@arm.com>
2019-02-27	arm64: dts: rockchip: move QCA6174A wakeup pin into its USB node	Brian Norris
	Currently, we don't coordinate BT USB activity with our handling of the BT out-of-band wake pin, and instead just use gpio-keys. That causes problems because we have no way of distinguishing wake activity due to a BT device (e.g., mouse) vs. the BT controller (e.g., re-configuring wake mask before suspend). This can cause spurious wake events just because we, for instance, try to reconfigure the host controller's event mask before suspending. We can avoid these synchronization problems by handling the BT wake pin directly in the btusb driver -- for all activity up until BT controller suspend(), we simply listen to normal USB activity (e.g., to know the difference between device and host activity); once we're really ready to suspend the host controller, there should be no more host activity, and only then do we unmask the GPIO interrupt. This is already supported by btusb; we just need to describe the wake pin in the right node. We list 2 compatible properties, since both PID/VID pairs show up on Scarlet devices, and they're both essentially identical QCA6174A-based modules. Also note that the polarity was wrong before: Qualcomm implemented WAKE as active high, not active low. We only got away with this because gpio-keys always reconfigured us as bi-directional edge-triggered. Finally, we have an external pull-up and a level-shifter on this line (we didn't notice Qualcomm's polarity in the initial design), so we can't do pull-down. Switch to pull-none. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
2018-11-06	arm64: dts: rockchip: add Gru Scarlet devicetrees	Heiko Stuebner
	Gru-Scarlet is a tablet device using ChomeOS, dual-dsi display and Wacom touchscreen with stylus. There exist two variants in the market using different displays that are differentiated via their sku-id. The bootloader on them also determines the correct devicetree to load via the sku-id. So add a common scarlet dtsi and two minimal board devicetrees for the two display variants. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring <robh@kernel.org>