summaryrefslogtreecommitdiff
path: root/arch/arm/mach-ux500
AgeCommit message (Collapse)Author
2015-07-27irqchip/gic: Remove redundant gic_set_irqchip_flagsSudeep Holla
Now that the GIC chip implementation enables IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND by default, the platforms requiring them need not override the irqchip flags as before. This patch removes all the users of gic_set_irqchip_flags and the function itself. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Simon Horman <horms@verge.net.au> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1436971109-20189-2-git-send-email-sudeep.holla@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2015-07-25ARM: move heavy barrier support out of lineRussell King
The existing memory barrier macro causes a significant amount of code to be inserted inline at every call site. For example, in gpio_set_irq_type(), we have this for mb(): c0344c08: f57ff04e dsb st c0344c0c: e59f8190 ldr r8, [pc, #400] ; c0344da4 <gpio_set_irq_type+0x230> c0344c10: e3590004 cmp r9, #4 c0344c14: e5983014 ldr r3, [r8, #20] c0344c18: 0a000054 beq c0344d70 <gpio_set_irq_type+0x1fc> c0344c1c: e3530000 cmp r3, #0 c0344c20: 0a000004 beq c0344c38 <gpio_set_irq_type+0xc4> c0344c24: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344c28: e50bc034 str ip, [fp, #-52] ; 0xffffffcc c0344c2c: e12fff33 blx r3 c0344c30: e51bc034 ldr ip, [fp, #-52] ; 0xffffffcc c0344c34: e51b2030 ldr r2, [fp, #-48] ; 0xffffffd0 c0344c38: e5963004 ldr r3, [r6, #4] Moving the outer_cache_sync() call out of line reduces the impact of the barrier: c0344968: f57ff04e dsb st c034496c: e35a0004 cmp sl, #4 c0344970: e50b2030 str r2, [fp, #-48] ; 0xffffffd0 c0344974: 0a000044 beq c0344a8c <gpio_set_irq_type+0x1b8> c0344978: ebf363dd bl c001d8f4 <arm_heavy_mb> c034497c: e5953004 ldr r3, [r5, #4] This should reduce the cache footprint of this code. Overall, this results in a reduction of around 20K in the kernel size: text data bss dec hex filename 10773970 667392 10369656 21811018 14ccf4a ../build/imx6/vmlinux-old 10754219 667392 10369656 21791267 14c8223 ../build/imx6/vmlinux-new Another advantage to this approach is that we can finally resolve the issue of SoCs which have their own memory barrier requirements within multiplatform kernels (such as OMAP.) Here, the bus interconnects need additional handling to ensure that writes become visible in the correct order (eg, between dma_map() operations, writes to DMA coherent memory, and MMIO accesses.) Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2015-05-18ARM: ux500: delete static resource definesLinus Walleij
These macros were used in the past to define static resources, but are not used anymore and have no future, delete them. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: rename ux500_map_ioLinus Walleij
This function is not mapping any I/O other than for probing the chip ID. Rename it to make the function graspable. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: look up PRCMU resource from DTLinus Walleij
This removes the static map for the PRCMU in favor of looking up that resource from the device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: kill off L2CC static mapLinus Walleij
The l2x0 level 2 cache initialization used a static map to get at the l2x0 registers. Get rid of this by getting the register range from the device tree and just remap it for the short time we need it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: get rid of SCU and backupram static mapsLinus Walleij
After moving the SMP and PM code to use dynamic mappings from the device tree, we can delete the static maps for SCU and backup RAM. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: get rid of static GIC dist baseLinus Walleij
The GIC distributor was mapped statically for the PM code but the driver already get the base address from the DT. Augment the PM code to get the base from the device tree and remove the static map. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: get SCU base from device treeLinus Walleij
The SMP startup/shutdown code relied on a static SCU base address, let's get this from the device tree instead. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: remap BB offset dynamicallyLinus Walleij
Instead of relying on static maps, remap the BB chip ID offset dynamically. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: remove static maps from platsmpLinus Walleij
This removes the reliance on static maps for SCU and backupram for the SMP startup of the Ux500 SoC. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18ARM: ux500: delete UART static mapLinus Walleij
Delete the static maps for the Ux500 UARTs and rely on debug_ll_io_init() to do the trick. commit f87b95dd2e4a8832b1d6034f15a5324db42608a0 "ARM: ux500: move debugmacro to debug includes" defined the necessary addruart macro two years ago. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-13ARM: ux500: get rid of static mapsLinus Walleij
The static mappings of the GPIO blocks, clock/reset controller and MTU timer are clearly superfluous. These are all probed exclusively from the device tree. Tested on the U8500. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-03-15ARM: ux500: switch from gic_arch_extn to gic_set_irqchip_flagsMarc Zyngier
Instead of directly touching gic_arch_extn, which is about to be removed, use gic_set_irqchip_flags instead. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088737-15817-4-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2015-02-19ARM: make of_device_ids constUwe Kleine-König
of_device_ids (i.e. compatible strings and the respective data) are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs in arch/arm as const, too. While at it also add some __initconst annotations. Acked-by: Jason Cooper <jason@lakedameon.net> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-10-28ARM: ux500: Enable Kconfig for the generic PM domainUlf Hansson
Since ux500 uses the generic PM domain, let's enable the corresponding Kconfig as long as CONFIG_PM also is enabled. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-28ARM: ux500: Initial support for PM domainsUlf Hansson
The ux500 SoC uses the generic PM domain and requires the domains to be specified through DT. Currently the genpd callbacks for handling power gating|ungating are implemented as dummy functions. To be able to enable those to perform PM domain gating/ungating, each device that resides in the VAPE domain must be properly handled from a runtime PM perspective. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-10ARM: ux500: remove pointless cache setup complexityLinus Walleij
This cleans out non-DT cache setup (the ux500 is DT only), and sinks the l2cc base into the unlock function. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-10ARM: ux500: storage class should be before const qualifierTobias Klauser
The C99 specification states in section 6.11.5: The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-10ARM: ux500: Staticize ab8505_regulatorsSachin Kamat
'ab8505_regulators' is used only in this file. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-10ARM: ux500: Staticize local symbols in cpu-db8500.cSachin Kamat
Symbols local to this file are made static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-10ARM: ux500: Staticise ux500_soc_attrThierry Reding
This variable is not used outside of the file that it's declared in, so reduce the scope to the local file. Signed-off-by: Thierry Reding <treding@nvidia.com> [Also add const marker after suggestion from Lee Jones] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-24Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-armLinus Torvalds
Pull ARM fixes from Russell King: "A number of low impact fixes, the most noticable one is the thumb2 frame pointer fix. We also fix a regression caused during this merge window with ARM925 CPUs running with caches disabled, and fix a number of warnings" * 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: arm925: ensure assembly sets up writethrough mapping ARM: perf: fix compiler warning with gcc 4.6.4 (and tidy code) ARM: l2c: fix dependencies on PL310 errata symbols ARM: 8069/1: Make thread_save_fp macro aware of THUMB2 mode ARM: 8068/1: scoop: Remove unused variable
2014-06-19ARM: l2c: fix dependencies on PL310 errata symbolsRussell King
A number of configurations spit out warnings similar to: warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_588369 which has unmet direct dependencies (CACHE_L2X0) warning: (SOC_IMX6 && SOC_VF610 && ARCH_OMAP4) selects PL310_ERRATA_727915 which has unmet direct dependencies (CACHE_L2X0) Clean up the dependencies here: * PL310 symbols should only be selected when CACHE_L2X0 is enabled. * Since the cache-l2x0 code detects PL310 presence at runtime, and we will eventually get rid of CACHE_PL310, surround these errata options with an if CACHE_L2X0 conditional rather than repeating the dependency against each. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-06-17ARM: use menuconfig for sub-arch menusRob Herring
The System Type menu is getting quite long with platforms and is inconsistent in handling of sub-arch specific options. Tidy up the menu by making platform options a menuconfig entry containing any platform specific config items. [arnd: change OMAP part according to suggestion from Tony Lindgren <tony@atomide.com>] Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-06-17ARM: Remove ARCH_HAS_CPUFREQ config optionStephen Boyd
This config exists entirely to hide the cpufreq menu from the kernel configuration unless a platform has selected it. Nothing is actually built if this config is 'Y' and it just leads to more patches that add a select under a platform Kconfig so that some other CPUfreq option can be chosen. Let's remove the option so that we can always enable CPUfreq drivers on ARM platforms. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-06-05Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into nextLinus Torvalds
Pull ARM updates from Russell King: - Major clean-up of the L2 cache support code. The existing mess was becoming rather unmaintainable through all the additions that others have done over time. This turns it into a much nicer structure, and implements a few performance improvements as well. - Clean up some of the CP15 control register tweaks for alignment support, moving some code and data into alignment.c - DMA properties for ARM, from Santosh and reviewed by DT people. This adds DT properties to specify bus translations we can't discover automatically, and to indicate whether devices are coherent. - Hibernation support for ARM - Make ftrace work with read-only text in modules - add suspend support for PJ4B CPUs - rework interrupt masking for undefined instruction handling, which allows us to enable interrupts earlier in the handling of these exceptions. - support for big endian page tables - fix stacktrace support to exclude stacktrace functions from the trace, and add save_stack_trace_regs() implementation so that kprobes can record stack traces. - Add support for the Cortex-A17 CPU. - Remove last vestiges of ARM710 support. - Removal of ARM "meminfo" structure, finally converting us solely to memblock to handle the early memory initialisation. * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits) ARM: ensure C page table setup code follows assembly code (part II) ARM: ensure C page table setup code follows assembly code ARM: consolidate last remaining open-coded alignment trap enable ARM: remove global cr_no_alignment ARM: remove CPU_CP15 conditional from alignment.c ARM: remove unused adjust_cr() function ARM: move "noalign" command line option to alignment.c ARM: provide common method to clear bits in CPU control register ARM: 8025/1: Get rid of meminfo ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type ARM: 8066/1: correction for ARM patch 8031/2 ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation ARM: 8065/1: remove last use of CONFIG_CPU_ARM710 ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction ARM: 8047/1: rwsem: use asm-generic rwsem implementation ARM: l2c: trial at enabling some Cortex-A9 optimisations ARM: l2c: add warnings for stuff modifying aux_ctrl register values ARM: l2c: print a warning with L2C-310 caches if the cache size is modified ARM: l2c: remove old .set_debug method ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this ...
2014-05-30ARM: l2c: ux500: don't try to change the L2 cache auxiliary control registerRussell King
ux500 can't change the auxiliary control register, so there's no point passing values to try and modify it to the l2x0 init functions. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: ux500: remove cache size overrideRussell King
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: ux500: implement dummy write_sec methodRussell King
ux500 can't write to any of the secure registers on the L2C controllers, so provide a dummy handler which ignores all writes. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30ARM: l2c: fix register namingRussell King
We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-12ARM: ux500: Remove redundant board file for mmci platform dataUlf Hansson
Since all platform data has been transfered to DT, we don't need the container for the mmci platform data anymore. Remove the file and the corresponding references to it's data. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-05Merge tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds
Pull ARM SoC device tree changes from Arnd Bergmann: "A large part of the arm-soc patches are nowadays DT changes, adding support for new SoCs, boards and devices without changing kernel source. The plan is still to move the devicetree files out of the kernel tree and reduce the amount of churn going on here, but we keep finding reasons to delay doing that. Changes are really all over the place, with little sticking out particularly. We have contributions from a total of 116 people in this branch. Unfortunately, the size of this branch also causes a significant number of conflicts at the moment, typically when subsystem maintainers merge patches that change the driver at the same time as the dts files. In most cases this could be avoided because the dts changes are supposed to be compatible in both ways, and we are asking everyone to send ARM dts changes through our tree only" * tag 'dt-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (541 commits) dts: stmmac: Document the clocks property in the stmmac base document dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. ARM: STi: stih41x: Add support for the FSM Serial Flash Controller ARM: STi: stih416: Add support for the FSM Serial Flash Controller ARM: tegra: fix Dalmore pinctrl configuration ARM: dts: keystone: use common "ti,keystone" compatible instead of -evm ARM: dts: k2hk-evm: set ubifs partition size for 512M NAND ARM: dts: Build all keystone dt blobs ARM: dts: keystone: Fix control register range for clktsip ARM: dts: keystone: Fix domain register range for clkfftc1 ARM: dts: bcm28155-ap: leave camldo1 on to fix reboot ARM: dts: add bcm590xx pmu support and enable for bcm28155-ap ARM: dts: bcm21664: Add device tree files. ARM: DT: bcm21664: Device tree bindings ARM: efm32: properly namespace i2c location property ARM: efm32: fix unit address part in USART2 device nodes' names ARM: mvebu: Enable NAND controller in Armada 385-DB ARM: mvebu: Add support for NAND controller in Armada 38x SoC ARM: mvebu: Add the Core Divider clock to Armada 38x SoCs ARM: mvebu: Add a 2 GHz fixed-clock on Armada 38x SoCs ...
2014-03-04mfd: dbx500/abx500: root out hardcoded IRQ assignmentsLinus Walleij
The DBx500 and ABx500 should be getting their IRQs from the device tree and nowhere else. Get rid of all the static assignments everywhere, delete it from the driver, platform data and the board files in one swift strike. Lots of cross-dependencies in the MFD drivers for PRCMU and AB8500 makes it necessary to strike everywhere at once to eradicate IRQs passed as resources and platform data to the left and right around the platform. Cc: Mark Brown <broonie@kernel.org> Cc: Samuel Ortiz <sameo@linux.intel.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-04ARM: ux500: drop a chunk of GPIO definitionsLinus Walleij
The Ux500 GPIOs are now assigned dynamically from the device tree. Drop this table of static assignments. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-28ARM: ux500: skip GIC CPU and dist address checksLinus Walleij
The Ux500 is initializing its IRQs from the device tree and does not need to figure out any static base addresses anymore, this is just dead code so delete it. Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-28ARM: ux500: delete pointless DT config optionLinus Walleij
Supporting device tree on the Ux500 is not optional anymore, so delete the config option and compile this in at all times. Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-19ARM: select MIGHT_HAVE_CACHE_L2X0 for V6 and V7 multi-platformRob Herring
Many V6 and V7 platforms have an L2x0 cache, so make CONFIG_MIGHT_HAVE_CACHE_L2X0 visible for V6 and V7 multi-platform builds. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-02-19ARM: select HAVE_SMP for V7 multi-platformRob Herring
All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7 multi-platform builds. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-02-19ARM: centralize common multi-platform kconfig optionsRob Herring
Multi-platform requires various kconfig options to be selected, so platforms don't need to select them individually. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-02-04ARM: ux500: move last AB8505 set-up to DTLinus Walleij
This moves the set-up of the HREF500 with its AB8505 ASIC to a device tree include. Since there is not yet any device tree for this board the DTSI is currently unused. After this delete the board file for pins for good and migration of pins to the device tree is complete. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 clock out pins to DTLinus Walleij
This moves the AB8500 pin settings for the clock out pins over to the device tree. We can delete the special setup calls for the platforms only using the AB8500 and not AB8505. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 modem I2C settings to DTLinus Walleij
This moves the pin setup of the AB8500 modem I2C pins (SCL/SDA) from the board file to the device tree. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 EXTCPENA from board file to DTLinus Walleij
This moves the configuration of the AB8500 EXTCPENA pin from the board file to the device tree. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 DMIC settings to DTLinus Walleij
This move the AB8500 DMIC (microphone) pin setup from the board file to the device tree. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 USB UICC settings to DTLinus Walleij
This moves the set-up of the USB UICC (InteChip USB) from the board file to the device tree. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 audio interface 1 settings to DTLinus Walleij
This moves the pin muxing and configuration for audio interface one over to the device tree as a hog configuration. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 PWM out settings to device treeLinus Walleij
This moves the muxing and biasing of the AB8500 PWM output pins over to the device tree for affected platforms. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 YCBCR settings to device treeLinus Walleij
This moves the pin control settings for the YCBCR connector on the AB8500 over to the device tree as a hog. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-04ARM: ux500: move AB8500 GPIOs to device treeLinus Walleij
Move the AB8500 muxing and biasing settings over from the board file to the device tree, include it in the reference designs using the AB8500: HREF prior to v60, v60plus and Snowball. Set up these GPIO lines using hogs, just like in the board file. Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 00:12:44 +0000