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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver changes from Olof Johansson:
"This is a rather large set of patches for device drivers that for one
reason or another the subsystem maintainer preferred to get merged
through the arm-soc tree. There are both new drivers as well as
existing drivers that are getting converted from platform-specific
code into standalone drivers using the appropriate subsystem specific
interfaces.
In particular, we can now have pinctrl, clk, clksource and irqchip
drivers in one file per driver, without the need to call into platform
specific interface, or to get called from platform specific code, as
long as all information about the hardware is provided through a
device tree.
Most of the drivers we touch this time are for clocksource. Since now
most of them are part of drivers/clocksource, I expect that we won't
have to touch these again from arm-soc and can let the clocksource
maintainers take care of these in the future.
Another larger part of this series is specific to the exynos platform,
which is seeing some significant effort in upstreaming and
modernization of its device drivers this time around, which
unfortunately is also the cause for the churn and a lot of the merge
conflicts.
There is one new subsystem that gets merged as part of this series:
the reset controller interface, which is a very simple interface for
taking devices on the SoC out of reset or back into reset. Patches to
use this interface on i.MX follow later in this merge window, and we
are going to have other platforms (at least tegra and sirf) get
converted in 3.11. This will let us get rid of platform specific
callbacks in a number of platform independent device drivers."
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (256 commits)
irqchip: s3c24xx: add missing __init annotations
ARM: dts: Disable the RTC by default on exynos5
clk: exynos5250: Fix parent clock for sclk_mmc{0,1,2,3}
ARM: exynos: restore mach/regs-clock.h for exynos5
clocksource: exynos_mct: fix build error on non-DT
pinctrl: vt8500: wmt: Fix checking return value of pinctrl_register()
irqchip: vt8500: Convert arch-vt8500 to new irqchip infrastructure
reset: NULL deref on allocation failure
reset: Add reset controller API
dt: describe base reset signal binding
ARM: EXYNOS: Add arm-pmu DT binding for exynos421x
ARM: EXYNOS: Add arm-pmu DT binding for exynos5250
ARM: EXYNOS: Enable PMUs for exynos4
irqchip: exynos-combiner: Correct combined IRQs for exynos4
irqchip: exynos-combiner: Add set_irq_affinity function for combiner_irq
ARM: EXYNOS: fix compilation error introduced due to common clock migration
clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
clk: exynos4: export clocks required for fimc-is
clk: samsung: Fix compilation error
clk: tegra: fix enum tegra114_clk to match binding
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git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c changes from Wolfram Sang:
- an arbitration driver. While the driver is quite simple, it caused
discussion if we need additional arbitration on top of the one
specified in the I2C standard. Conclusion is that I accept a few
generic mechanisms, but not very specific ones.
- the core lost the detach_adapter() call. It has no users anymore and
was in the way for other cleanups. attach_adapter() is sadly still
there since there are users waiting to be converted.
- the core gained a bus recovery infrastructure. I2C defines a way to
recover if the data line is stalled. This mechanism is now in the
core and drivers can now pass some data to make use of it.
- bigger driver cleanups for designware, s3c2410
- removing superfluous refcounting from drivers
- removing Ben Dooks as second maintainer due to inactivity. Thanks
for all your work so far, Ben!
- bugfixes, feature additions, devicetree fixups, simplifications...
* 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (38 commits)
i2c: xiic: must always write 16-bit words to TX_FIFO
i2c: octeon: use HZ in timeout value
i2c: octeon: Fix i2c fail problem when a process is terminated by a signal
i2c: designware-pci: drop superfluous {get|put}_device
i2c: designware-plat: drop superfluous {get|put}_device
i2c: davinci: drop superfluous {get|put}_device
MAINTAINERS: Ben Dooks is inactive regarding I2C
i2c: mux: Add i2c-arb-gpio-challenge 'mux' driver
i2c: at91: convert to dma_request_slave_channel_compat()
i2c: mxs: do error checking and handling in PIO mode
i2c: mxs: remove races in PIO code
i2c-designware: switch to use runtime PM autosuspend
i2c-designware: use usleep_range() in the busy-loop
i2c-designware: enable/disable the controller properly
i2c-designware: use dynamic adapter numbering on Lynxpoint
i2c-designware-pci: use managed functions pcim_* and devm_*
i2c-designware-pci: use dev_err() instead of printk()
i2c-designware: move to managed functions (devm_*)
i2c: remove CONFIG_HOTPLUG ifdefs
i2c: s3c2410: Add SMBus emulation for block read
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The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.
The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.
To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Expose Tegra chip ID and revision in /sys/devices/soc for user mode
usage
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Unify board-dt-tegra{30,114} to the Tegra20 DT board file, "tegra.c".
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This is the preparation to unify "board-dt-tegra{20,30,114}.c" to a
single file "tegra.c".
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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