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We removed __cpuinit support (leaving no-op stubs) quite some time ago.
However this one crept back in as of commit a7a2b3118b410fb3cd3a8363b1
("ARM: rockchip: add smp bringup code").
Since we want to clobber the stubs soon, get this removed now.
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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http://ftp.arm.linux.org.uk/pub/armlinux/kernel/git-cur/linux-2.6-arm into next/cleanup
* 'for-arm-soc' of http://ftp.arm.linux.org.uk/pub/armlinux/kernel/git-cur/linux-2.6-arm:
ARM: fix EFM32 build breakage caused by cpu_resume_arm
ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state
ARM: v7 setup function should invalidate L1 cache
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All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.
This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.
ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.
Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This reverts commit b403125d3bbf8046c1186e1a49cb17bb5551db14.
As reported by Chris, both commits
b403125 "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"
0ea001d "ARM: rockchip: disable dapswjdp during suspend"
actually fix the same issue and b403125 is the older one, which got
superseded by 0ea001d. Therefore revert the obsolete one again.
Reported-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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timer7 supplies the architected timer and thus as has to run when
the system clocksource and clockevents drivers are registered.
While it should be the responsibility of the bootloader to do this,
and there exists a fix in a community u-boot, all u-boot based systems
that actually shipped have the mentioned issue.
Therefore to not require every developer to update their u-boot, add a
snippet for this, enabling the timer early in the kernel.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Sometimes the debug module may not work well after resume, since it has
not been correctly reset when wakeup from suspend. That cause system
crash during reusme, and a 'undefined instruction' is displayed on the
console. Set the GRF_FORCE_JTAG bit of RK3288_GRF_SOC_CON0 can ensure
that debug modul is reset. And we can change the value of
RK3288_GRF_SOC_CON0 back when system resume.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
According to discussions, there does not seem a better solution available.
Please also see the potential security implication described in the
comment inline in the code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Reset dapswjdp is controlled by JTAG_TRSTN, if the iomux of this pin is
not "jtag_trstn". the AP would think this pin is always high, so it can
not reset before resume. When system resume, but the dapswjdp is not in
a default state, it may Access some illegal address, it cause system
crash during resume.
Let's disable this jtag function by clear the dapdeviceen bit, it
prohibit the dapswjdp to access memory and registers. This bit would
be enable in MASKROM, so we need clear it in suspend everytime.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The watchdog clock should be disable in dw_wdt_suspend, but we set a
dummy clock to watchdog for rk3288. So the watchdog will continue to
work during suspend. And we switch the system clock to 32khz from 24Mhz,
during suspend, so the watchdog timer over count will increase to
755 times, about 12.5 hours, the original value is 60 seconds. So
watchdog will reset the system over a night, but voltage are all
incorrect, then it hang on reset.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The register-default delay time for wait the 24MHz OSC stabilization as well
as PMU stabilization is 750ms, let's decrease them to a still safe 30ms.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The regmap_config struct may be const because it is not modified by the
driver and regmap_init() accepts pointer to const.
Make function rockchip_get_core_reset() static because it is not used
outside of the platsmp.c file.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The rockchips suspend/resume code requires regulators to work,
and gives a compile-time error if they are not available:
arch/arm/mach-rockchip/built-in.o: In function `rk3288_suspend_finish':
:(.text+0x146): undefined reference to `regulator_suspend_finish'
arch/arm/mach-rockchip/built-in.o: In function `rk3288_suspend_prepare':
:(.text+0x18e): undefined reference to `regulator_suspend_prepare'
To solve this, we now enable regulators whenever they are needed,
which is what we do on a lot of other platforms as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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If CONFIG_PM_SLEEP is disabled, we get a build error for rockchips:
arch/arm/mach-rockchip/built-in.o: In function `rockchip_dt_init':
:(.init.text+0x1c): undefined reference to `rockchip_suspend_init'
This adds an inline alternative for that case.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"New and updated SoC support. Also included are some cleanups where
the platform maintainers hadn't separated cleanups from new developent
in separate branches.
Some of the larger things worth pointing out:
- A large set of changes from Alexandre Belloni and Nicolas Ferre
preparing at91 platforms for multiplatform and cleaning up quite a
bit in the process.
- Removal of CSR's "Marco" SoC platform that never made it out to the
market. We love seeing these since it means the vendor published
support before product was out, which is exactly what we want!
New platforms this release are:
- Conexant Digicolor (CX92755 SoC)
- Hisilicon HiP01 SoC
- CSR/sirf Atlas7 SoC
- ST STiH418 SoC
- Common code changes for Nvidia Tegra132 (64-bit SoC)
We're seeing more and more platforms having a harder time labelling
changes as cleanups vs new development -- which is a good sign that
we've come quite far on the cleanup effort. So over time we might
start combining the cleanup and new-development branches more"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
ARM: at91/trivial: unify functions and machine names
ARM: at91: remove at91_dt_initialize and machine init_early()
ARM: at91: change board files into SoC files
ARM: at91: remove at91_boot_soc
ARM: at91: move alternative initial mapping to board-dt-sama5.c
ARM: at91: merge all SOC_AT91SAM9xxx
ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
ARM: digicolor: select syscon and timer
ARM: zynq: Simplify SLCR initialization
ARM: zynq: PM: Fixed simple typo.
ARM: zynq: Setup default gpio number for Xilinx Zynq
ARM: digicolor: add low level debug support
ARM: initial support for Conexant Digicolor CX92755 SoC
ARM: OMAP2+: Add dm816x hwmod support
ARM: OMAP2+: Add clock domain support for dm816x
ARM: OMAP2+: Add board-generic.c entry for ti81xx
ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
ARM: at91: remove unused mach/system_rev.h
ARM: at91: stop using HAVE_AT91_DBGUx
ARM: at91: fix ordering of SRAM and PM initialization
...
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The rk3288 board uses the architected timers and these ones are shutdown when
the cpu is powered down. There is a need of a broadcast timer in this case to
ensure proper wakeup when the cpus are in sleep mode and a timer expires.
This driver provides the basic timer functionnality as a backup for the local
timers at sleep time.
The timer belongs to the alive subsystem. It includes two programmables 64 bits
timer channels but the driver only uses 32bits. It works with two operations
mode: free running and user defined count.
Programing sequence:
1. Timer initialization:
* Disable the timer by writing '0' to the CONTROLREG register
* Program the timer mode by writing the mode to the CONTROLREG register
* Set the interrupt mask
2. Setting the count value:
* Load the count value to the registers COUNT0 and COUNT1 (not used).
3. Enable the timer
* Write '1' to the CONTROLREG register with the mode (free running or user)
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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The Rockchip support is not limited to Cortex-A9 socs anymore and its
presence may confuse people reading /proc/cpuinfo. So remove the core
specific part.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
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rk3288 SoCs have a function to automatically switch between jtag/sdmmc pinmux
settings depending on the card state. This collides with a lot of assumptions.
It only works when using the internal card-detect mechanism and breaks
horribly when using either the normal card-detect via the slot-gpio function
or via any other pin. Also there is of course no link between the mmc and jtag
on the software-side, so the jtag clocks may very well be disabled when the
card is ejected and the soc switches back to the jtag pinmux.
Leaving the switching function enabled did result in mmc timeouts and rcu
stalls thus hanging the system on 3.19-rc1. Therefore disable it in all cases,
as we expect the devicetree to explicitly select either mmc or jtag pinmuxes
anyway.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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It's a basic version of suspend and resume for rockchip,
it only support RK3288 now.
Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This patch add basic rk3288 smp support.
Only cortex-A9 need invalid L1, A7/A12/A15/A17 should not invalid L1, since
for A7/A12/A15, the invalidation would be taken as clean and invalidate.
If you use the software manual invalidation instead of hardware invalidation
(assert l1/l2rstdisable during reset) after reset, there is tiny change that
some cachelines would be in dirty and valid state after reset(since the ram
content would be random value after reset), then the unexpected clean might
lead to system crash.
It is a known issue for the A12/A17 MPCore multiprocessor that the active
processors might be stalled when the individual processor is powered down,
we can avoid this prolbem by softreset the processor before power it down.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.
The old way of finding the pmu stays of course available.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The pmu register space is - like the GRF - shared by quite some peripherals.
On the rk3188 and rk3288 even parts of the pinctrl are living there.
Therefore we normally shouldn't map it a second time when the syscon
does this already.
Therefore convert the cpu power-domain handling to access the pmu via a
regmap and at first try to get it via the syscon interface.
Getting this syscon will only fail if the pmu node does not have the
"syscon" compatible and thus does not get shared with other drivers.
In this case we map it like before and create the necessary regmap on
top of it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc
Merge "ARM: rockchip: cpufreq-cpu0 device" from Heiko Stubner:
Add cpufreq-dt platform device for cpu frequency scaling.
* tag 'v3.18-rockchip-cpufreqdev-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: rockchip: honor renaming of cpufreq-cpu0 to cpufreq-dt
ARM: rockchip: add a cpufreq-cpu0 device
Signed-off-by: Olof Johansson <olof@lixom.net>
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cpufreq-cpu0 got renamed to a more generic name cpufreq-dt, so
adapt the created platform-device to this.
Reported-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Rockchip SoCs can sucessfully use the generic cpufreq-cpu0 driver to
do frequency scaling. Therefore add a platform device in the machine
init code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This is needed to access the pl330 dma controllers on Rockchip SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree changes from Olof Johansson:
"Unlike the board branch, this keeps having large sets of changes for
every release, but that's quite expected and is so far working well.
Most of this is plumbing for various device bindings and new
platforms, but there's also a bit of cleanup and code removal for
things that are moved from platform code to DT contents (some OMAP
clock code in particular).
There's also a pinctrl driver for tegra here (appropriately acked),
that's introduced this way to make it more bisectable.
I'm happy to say that there were no conflicts at all with this branch
this release, which means that changes are flowing through our tree as
expected instead of merged through driver maintainers (or at least not
done with conflicts).
There are several new boards added, and a couple of SoCs. In no
particular order:
- Rockchip RK3288 SoC support, including DTS for a dev board that
they have seeded with some community developers.
- Better support for Hardkernel Exynos4-based ODROID boards.
- CCF conversions (and dtsi contents) for several Renesas platforms.
- Gumstix Pepper (TI AM335x) board support
- TI eval board support for AM437x
- Allwinner A23 SoC, very similar to existing ones which mostly has
resulted in DT changes for support. Also includes support for an
Ippo tablet with the chipset.
- Allwinner A31 Hummingbird board support, not to be confused with
the SolidRun i.MX-based Hummingboard.
- Tegra30 Apalis board support"
* tag 'dt-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (334 commits)
ARM: dts: Enable USB host0 (EHCI) on rk3288-evb
ARM: dts: add rk3288 ehci usb devices
ARM: dts: Turn on USB host vbus on rk3288-evb
ARM: tegra: apalis t30: fix device tree compatible node
ARM: tegra: paz00: Fix some indentation inconsistencies
ARM: zynq: DT: Clarify Xilinx Zynq platform
ARM: dts: rockchip: add watchdog node
ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
ARM: dts: Add missing pinctrl for uart0/1 for exynos3250
ARM: dts: Remove duplicate 'interrput-parent' property for exynos3250
ARM: dts: Add TMU dt node to monitor the temperature for exynos3250
ARM: dts: Specify MAX77686 pmic interrupt for exynos5250-smdk5250
ARM: dts: cypress,cyapa trackpad is exynos5250-Snow only
ARM: dts: max77686 is exynos5250-snow only
ARM: zynq: DT: Remove DMA from board DTs
ARM: zynq: DT: Add CAN node
ARM: EXYNOS: Add exynos5260 PMU compatible string to DT match table
ARM: dts: Add PMU DT node for exynos5260 SoC
ARM: EXYNOS: Add support for Exynos5410 PMU
ARM: dts: Add PMU to exynos5410
...
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git://git.linaro.org/people/mike.turquette/linux into next/soc
This is a dependency for the rk3288 DT updates, the branch should
first get merged through Mike's clk git.
* 'clk-rockchip' of git://git.linaro.org/people/mike.turquette/linux:
ARM: rockchip: Select ARCH_HAS_RESET_CONTROLLER
clk: rockchip: add clock controller for rk3288
dt-bindings: add documentation for rk3288 cru
clk: rockchip: add clock driver for rk3188 and rk3066 clocks
dt-bindings: add documentation for rk3188 clock and reset unit
clk: rockchip: add reset controller
clk: rockchip: add clock type for pll clocks and pll used on rk3066
clk: rockchip: add basic infrastructure for clock branches
clk: composite: improve rate_hw sanity check logic
clk: composite: allow read-only clocks
clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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Adds ability to shutdown all CPUs except the first one
(since it might be special for a lot of platforms).
It is now possible to use kexec which requires such a feature.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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When compiling for multiplatform for both ARMv6 and ARMv7, the default
compiler flags are for ARMv6, and the following cpu-hotplug change will
fail with:
/tmp/ccSFxfmI.s:68: Error: selected processor does not support ARM mode `isb '
/tmp/ccSFxfmI.s:74: Error: selected processor does not support ARM mode `isb '
/tmp/ccSFxfmI.s:75: Error: selected processor does not support ARM mode `dsb '
Fix this in a similar manner as in commit 9f0affcf3e21 "ARM: mvebu: Fix pmsu
compilation when ARMv6 is selected", by specifying ARMv7 flags for platsmp.o.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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All known Rockchip SoCs have a reset controller in their CRUs, so it's
helpful to have the reset controller framework selected by default,
only be deselected by the user in special cases.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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Pull ARM updates from Russell King:
- Major clean-up of the L2 cache support code. The existing mess was
becoming rather unmaintainable through all the additions that others
have done over time. This turns it into a much nicer structure, and
implements a few performance improvements as well.
- Clean up some of the CP15 control register tweaks for alignment
support, moving some code and data into alignment.c
- DMA properties for ARM, from Santosh and reviewed by DT people. This
adds DT properties to specify bus translations we can't discover
automatically, and to indicate whether devices are coherent.
- Hibernation support for ARM
- Make ftrace work with read-only text in modules
- add suspend support for PJ4B CPUs
- rework interrupt masking for undefined instruction handling, which
allows us to enable interrupts earlier in the handling of these
exceptions.
- support for big endian page tables
- fix stacktrace support to exclude stacktrace functions from the
trace, and add save_stack_trace_regs() implementation so that kprobes
can record stack traces.
- Add support for the Cortex-A17 CPU.
- Remove last vestiges of ARM710 support.
- Removal of ARM "meminfo" structure, finally converting us solely to
memblock to handle the early memory initialisation.
* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits)
ARM: ensure C page table setup code follows assembly code (part II)
ARM: ensure C page table setup code follows assembly code
ARM: consolidate last remaining open-coded alignment trap enable
ARM: remove global cr_no_alignment
ARM: remove CPU_CP15 conditional from alignment.c
ARM: remove unused adjust_cr() function
ARM: move "noalign" command line option to alignment.c
ARM: provide common method to clear bits in CPU control register
ARM: 8025/1: Get rid of meminfo
ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type
ARM: 8066/1: correction for ARM patch 8031/2
ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation
ARM: 8065/1: remove last use of CONFIG_CPU_ARM710
ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction
ARM: 8047/1: rwsem: use asm-generic rwsem implementation
ARM: l2c: trial at enabling some Cortex-A9 optimisations
ARM: l2c: add warnings for stuff modifying aux_ctrl register values
ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
ARM: l2c: remove old .set_debug method
ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this
...
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Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. This also allows us to eliminate the
.init_machine function as this becomes the same as the generic version.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
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They're u32, they're not unsigned long. The UL suffix is not required
here.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The error emitted when mapping the pmu failed, wrongly mentions the sram.
Reported-by: Kent Borg <kentborg@borg.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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into next/soc
i.MX SoC changes for 3.15 from Shawn Guo:
- Support suspend from ocram (DDR IO floating) for imx6 platforms
- Add cpuidle support for imx6sl
- Sparse warning fixes for imx6sl and vf610 clock code
- Remove PWM platform code
- Support ptp and rmii clock from pad
- Support WEIM CS GPR configuration
- Random cleanups and defconfig updates
* tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits)
ARM: imx6: drop .text.head section annotation from headsmp.S
ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6
ARM: imx6: rename pm-imx6q.c to pm-imx6.c
ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff
ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND
ARM: imx6: call suspend_set_ops() from suspend routine
ARM: imx6: build headsmp.o only on CONFIG_SMP
ARM: imx6: move v7_cpu_resume() into suspend-imx6.S
ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
bus: imx-weim: support CS GPR configuration
ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53
ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS
ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level
ARM: imx: add speed grading check for i.mx6 soc
ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
ARM: imx6q: support ptp and rmii clock from pad
ARM: imx6q: remove unneeded clk lookups
ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
...
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This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.
We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done later.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
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This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Ulrich Prinz <ulrich.prinz@googlemail.com>
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All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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Multi-platform requires various kconfig options to be selected, so
platforms don't need to select them individually.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC board updates from Olof Johansson:
"Board-related updates. This branch is getting smaller and smaller,
which is the whole idea so that's reassuring.
Right now by far most of the code is related to shmobile updates, and
they are now switching over to removal of board code and migration to
multiplatform, so we'll see their board code base shrink in the near
future too, I hope.
In addition to that is some defconfig updates, some display updates
for OMAP and a bit of new board support for Rockchip boards"
* tag 'boards-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (56 commits)
ARM: rockchip: add support for rk3188 and Radxa Rock board
ARM: rockchip: add dts for bqcurie2 tablet
ARM: rockchip: enable arm-global-timer
ARM: rockchip: move shared dt properties to common source file
ARM: OMAP2+: display: Create omap_vout device inside omap_display_init
ARM: OMAP2+: display: Create omapvrfb and omapfb devices inside omap_display_init
ARM: OMAP2+: display: Create omapdrm device inside omap_display_init
ARM: OMAP2+: drm: Don't build device for DMM
ARM: tegra: defconfig updates
RX-51: Add support for OMAP3 ROM Random Number Generator
ARM: OMAP3: RX-51: ARM errata 430973 workaround
ARM: OMAP3: Add secure function omap_smc3() which calling instruction smc #1
ARM: shmobile: marzen: enable INTC IRQ
ARM: shmobile: bockw: add SMSC support on reference
ARM: shmobile: Use SMP on Koelsch
ARM: shmobile: Remove KZM9D reference DTS
ARM: shmobile: Let KZM9D multiplatform boot with KZM9D DTB
ARM: shmobile: Remove non-multiplatform KZM9D reference support
ARM: shmobile: Use KZM9D without reference for multiplatform
ARM: shmobile: Sync KZM9D DTS with KZM9D reference DTS
...
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"This branch contains code cleanups, moves and removals for 3.13.
Qualcomm msm targets had a bunch of code removal for legacy non-DT
platforms. Nomadik saw more device tree conversions and cleanup of
old code. Tegra has some code refactoring, etc.
One longish patch series from Sebastian Hasselbarth changes the
init_time hooks and tries to use a generic implementation for most
platforms, since they were all doing more or less the same things.
Finally the "shark" platform is removed in this release. It's been
abandoned for a while and nobody seems to care enough to keep it
around. If someone comes along and wants to resurrect it, the removal
can easily be reverted and code brought back.
Beyond this, mostly a bunch of removals of stale content across the
board, etc"
* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (79 commits)
ARM: gemini: convert to GENERIC_CLOCKEVENTS
ARM: EXYNOS: remove CONFIG_MACH_EXYNOS[4, 5]_DT config options
ARM: OMAP3: control: add API for setting IVA bootmode
ARM: OMAP3: CM/control: move CM scratchpad save to CM driver
ARM: OMAP3: McBSP: do not access CM register directly
ARM: OMAP3: clock: add API to enable/disable autoidle for a single clock
ARM: OMAP2: CM/PM: remove direct register accesses outside CM code
MAINTAINERS: Add patterns for DTS files for AT91
ARM: at91: remove init_machine() as default is suitable
ARM: at91/dt: split sama5d3 peripheral definitions
ARM: at91/dt: split sam9x5 peripheral definitions
ARM: Remove temporary sched_clock.h header
ARM: clps711x: Use linux/sched_clock.h
MAINTAINERS: Add DTS files to patterns for Samsung platform
ARM: EXYNOS: remove unnecessary header inclusions from exynos4/5 dt machine file
ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
clk: nomadik: fix missing __init on nomadik_src_init
ARM: drop explicit selection of HAVE_CLK and CLKDEV_LOOKUP
ARM: S3C64XX: Kill CONFIG_PLAT_S3C64XX
ASoC: samsung: Use CONFIG_ARCH_S3C64XX to check for S3C64XX support
...
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RK2928 and RK3066 contain a dw_apb timer component, while the rk3188 uses
a slightly similar but still different timer component. But all of them
support the ARM-global-timer that got added as clocksource driver recently.
So enable support for it to get a working clocksource for rk3188.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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CONFIG_LOCAL_TIMERS was removed in february, so the twd never gets
selected. Fix this by making the twd depend on SMP directly.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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With arch/arm calling of_clk_init(NULL) from time_init(), we can now
remove custom .init_time hooks.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
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This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.
Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Olof Johansson <olof@lixom.net>
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