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All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.
This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.
ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.
Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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When compiling with "ARCH=arm" and "allmodconfig",
with commit: 9cdc99919a95e8b54c1998b65bb1bfdabd47d27b [2/7] ARM: hisi: enable MCPM implementation
we will get:
/tmp/cc6DjYjT.s: Assembler messages:
/tmp/cc6DjYjT.s:63: Error: selected processor does not support ARM mode `ubfx r1,r0,#8,#8'
/tmp/cc6DjYjT.s:761: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:762: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:769: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:775: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:776: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:795: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:801: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:802: Error: selected processor does not support ARM mode `dsb '
Fix platmcpm compilation when ARMv6 is selected.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Multiple CPU clusters are used in Hisilicon HiP04 SoC. Now use MCPM
framework to manage power on HiP04 SoC.
Changelog:
v20:
* Disable L2 prefetch when the whole cluster is down.
* Move disabling snoop filter into power_down() after L2 prefetch
disabled.
* Remove delay in wait_for_power_down() after L2 prefetch disabled.
* Add the sleep polling in wait_for_power_down() again since we
need to wait L2 when the cluster is down.
v19:
* Add comments on those delay hacks.
* Update on checking core enabled counts in wait_for_power_down().
v18:
* Fix to release resource in probe().
* Check whether cpu is already up in the process of making cpu down.
* Add udelay in power up/down sequence.
* Optimize on setting relocation entry.
* Optimize on polling status in wait_for_power_down().
* Add mcpm critical operations.
v17:
* Parse bootwrapper parameters in DTS file.
* Fix to use msleep() in spinlock region.
v16:
* Parse bootwrapper parameters in command line instead.
v13:
* Restore power down operation in MCPM.
* Fix disabling snoop filter issue in MCPM.
v12:
* Use wfi as power down state in MCPM.
* Remove wait_for_powerdown() in MCPM because wfi is used now.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Enable support for the Hisilicon HiX5HD2 SoC. This HiX5HD2 SoC series
support both single and dual Cortex-A9 cores.
Add ARCH_HIX5HD2 to distinguish HiX5HD2 from Hi3xxx.
They are different in implementation such as SMP, IPs integarted and
earlycon configure.
Signed-off-by: Haifeng Yan <yanhaifeng@gmail.com>
Signed-off-by: Jiancheng Xue <jchxue@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The hisi SMP code always uses the hi3xxx_set_cpu() function
defined in the hotplug.c file, so we cannot build without
this when CONFIG_SMP is enabled. This patch slightly restructures
the code so we always build the parts of hotplug.c that we need
but just leave out the CPU disable logic if CONFIG_HOTPLUG_CPU
is turned off.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
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Since some new Hisilicon SoCs are not named as hi3xxx, rename mach-hi3xxx
to mach-hisi instead. And the pronounciation of "hisi" is similar to the
chinese pronounciation of Hisilicon. So Hisilicon guys like this name.
ARCH_HI3xxx will be renamed later since other drivers are using it and
they are still in linux-next git tree. So rename ARCH_HI3xxx later.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
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