| Age | Commit message (Collapse) | Author |
|---|
|
Add the SMBus Controller DeviceIDs for the Intel DH89xxCC PCH.
Signed-off-by: Seth Heasley <seth.heasley@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
These are the extra 'Integrated Device Function' SMBus controllers found
on the Patsburg chipset. Mention the absence of slave mode support.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
Add support for the Intel Patsburg PCH SMBus Controller.
Signed-off-by: Seth Heasley <seth.heasley@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
Let the user disable selected features normally supported by the
device. This makes it possible to work around possible driver or
hardware bugs if the feature in question doesn't work as intended
for whatever reason.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Cc: Felix Rubinstein <felixru@gmail.com>
|
|
Add the Intel Cougar Point (PCH) SMBus controller device IDs.
Signed-off-by: Seth Heasley <seth.heasley@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
Adds the Intel Ibex Peak (PCH) SMBus Controller Device IDs.
Signed-off-by: Seth Heasley <seth.heasley@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
Add the Intel ICH10 SMBus Controller DeviceID's and updates
Tolapai support.
Signed-off-by: Jason Gaston <jason.d.gaston@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
I2C block read is supported since the ICH5. I couldn't get it to work
using the block buffer, so it's using the old-style byte-by-byte mode
for now.
Note: I'm also updating the driver author... The i2c-i801 driver was
really written by Mark Studebaker, even though he based his work on
the i2c-piix4 driver which was written by Philip Edelbrock.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
Add the Intel Tolapai SMBus Controller DID.
Signed-off-by: Jason Gaston <jason.d.gaston@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
Add an ability to utilize the internal SRAM buffer on ICH4
and newer host controllers to speed up execution of block operations.
I've split the code so that it is more clear which block transaction is
performed.
First of all the host controller's type is identified. isich4 is set when
we think that the controller has the internal buffer. Then, before every
block transaction, if isich4 is set, we attempt to enable the E32B bit in
SMBAUXCTL register.
Signed-off-by: Oleg Ryjkov <olegr@google.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
This is a frequently asked question so it deserves a paragraph in
the driver documentation.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
Add the Intel ICH9/ICH8/ESB2 SMBus Controller text to
i2c-i801 documentation.
Signed-off-by: Jason Gaston <jason.d.gaston@intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
|
|
i2c-i801: Remove force_addr parameter
Remove the force_addr module parameter. It doesn't appear to ever
have been needed, and PCI resources shouldn't be arbitrarily
changed anyway.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
|
|
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
|
