| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-02-13 | mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC) | Andrew Jeffery | |
| The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends on bits in both the System Control Unit and the LPC Host Controller. The Aspeed LPC Host Controller is described as a child node of the LPC host-range syscon device for arbitration of access by the host controller and pinmux drivers. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> | |||
| 2017-02-13 | mfd: dt: Add Aspeed Low Pin Count Controller bindings | Andrew Jeffery | |
| Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Lee Jones <lee.jones@linaro.org> | |||
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