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2021-02-08mmc: via-sdmmc: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-9-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: uniphier-sd: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-8-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: tifm_sd: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-7-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: s3cmci: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-6-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: omap: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-5-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: dw_mmc: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-4-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: au1xmmc: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-3-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: atmel-mci: Use new tasklet APIEmil Renner Berthing
This converts the driver to use the new tasklet API introduced in commit 12cc923f1ccc ("tasklet: Introduce new initialization API") Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Link: https://lore.kernel.org/r/20210204151847.91353-2-kernel@esmil.dk Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: cavium: Replace spin_lock_irqsave with spin_lock in hard IRQXiaofei Tan
It is redundant to do irqsave and irqrestore in hardIRQ context, where it has been in a irq-disabled context. Signed-off-by: Xiaofei Tan <tanxiaofei@huawei.com> Link: https://lore.kernel.org/r/1612422438-32525-1-git-send-email-tanxiaofei@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: queue: Remove unused defineChanWoo Lee
MMC_CQE_QUEUE_FULL is not set and is only cleared. Therefore, define is unnecessary. Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20210203072014.30272-1-cw9316.lee@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-08mmc: core: Drop redundant bouncesz from struct mmc_cardUlf Hansson
The commit de3ee99b097d ("mmc: Delete bounce buffer handling") removed the bounce buffer handling from the mmc core, but forgot to remove the bouncesz member from the struct mmc_card, let's fix it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20210202101626.64503-1-ulf.hansson@linaro.org
2021-02-08mmc: core: Drop redundant member in struct mmc hostUlf Hansson
The Kconfig option to use the blk-mq support was removed in commit 1bec43a3b181 ("mmc: core: Remove option not to use blk-mq"), but forgot to remove the use_blk_mq member in the struct mmc_host, let's fix it. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20210202101924.69970-1-ulf.hansson@linaro.org
2021-02-08mmc: core: Use host instead of card argument to mmc_spi_send_csd()Yue Hu
Since mmc_send_cxd_data() does not care card if opcode is MMC_SEND_CSD. Signed-off-by: Yue Hu <huyue2@yulong.com> Link: https://lore.kernel.org/r/20210201055507.542-1-zbestahu@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01Merge branch 'fixes' into nextUlf Hansson
2021-02-01mmc: core: Exclude unnecessary header fileChanWoo Lee
From the 4.19 kernel, thread related code has been removed in queue.c. So we can exclude unnecessary header file. Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com> Acked-by: Coly Li <colyli@suse.de> Link: https://lore.kernel.org/r/20210125064355.28545-1-cw9316.lee@samsung.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: mmci: Add support for probing bus voltage level translatorMarek Vasut
Add support for testing whether bus voltage level translator is present and operational. This is useful on systems where the bus voltage level translator is optional, as the translator can be auto-detected by the driver and the feedback clock functionality can be disabled if it is not present. This requires additional pinmux state, "init", where the CMD, CK, CKIN lines are not configured, so they can be claimed as GPIOs early on in probe(). The translator test sets CMD high to avoid interfering with a card, and then verifies whether signal set on CK is detected on CKIN. If the signal is detected, translator is present, otherwise the CKIN feedback clock are disabled. Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Ludovic Barre <ludovic.barre@st.com> Tested-by: Yann Gautier <yann.gautier@foss.st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20210124170258.32862-2-marex@denx.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: mmci: Add bindings to operate CMD, CK, CKIN pins as GPIOMarek Vasut
Add DT bindings to describe GPIO line associated with CMD, CK, CKIN pins. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Ludovic Barre <ludovic.barre@st.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210124170258.32862-1-marex@denx.de Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-msm: add Inline Crypto Engine supportEric Biggers
Add support for Qualcomm Inline Crypto Engine (ICE) to sdhci-msm. The standard-compliant parts, such as querying the crypto capabilities and enabling crypto for individual MMC requests, are already handled by cqhci-crypto.c, which itself is wired into the blk-crypto framework. However, ICE requires vendor-specific init, enable, and resume logic, and it requires that keys be programmed and evicted by vendor-specific SMC calls. Make the sdhci-msm driver handle these details. This is heavily inspired by the similar changes made for UFS, since the UFS and eMMC ICE instances are very similar. See commit df4ec2fa7a4d ("scsi: ufs-qcom: Add Inline Crypto Engine support"). I tested this on a Sony Xperia 10, which uses the Snapdragon 630 SoC, which has basic upstream support. Mainly, I used android-xfstests (https://github.com/tytso/xfstests-bld/blob/master/Documentation/android-xfstests.md) to run the ext4 and f2fs encryption tests in a Debian chroot: android-xfstests -c ext4,f2fs -g encrypt -m inlinecrypt These tests included tests which verify that the on-disk ciphertext is identical to that produced by a software implementation. I also verified that ICE was actually being used. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Satya Tangirala <satyat@google.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210126001456.382989-9-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01dt-bindings: mmc: sdhci-msm: add ICE registers and clockEric Biggers
Document the bindings for the registers and clock for the MMC instance of the Inline Crypto Engine (ICE) on Snapdragon SoCs. These bindings are needed in order for sdhci-msm to support inline encryption. Reviewed-by: Satya Tangirala <satyat@google.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210126001456.382989-8-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01firmware: qcom_scm: update comment for ICE-related functionsEric Biggers
The SCM calls QCOM_SCM_ES_INVALIDATE_ICE_KEY and QCOM_SCM_ES_CONFIG_SET_ICE_KEY are also needed for eMMC inline encryption support, not just for UFS. Update the comments accordingly. Reviewed-by: Satya Tangirala <satyat@google.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210125183810.198008-7-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: cqhci: add cqhci_host_ops::program_keyEric Biggers
On Snapdragon SoCs, the Linux kernel isn't permitted to directly access the standard CQHCI crypto configuration registers. Instead, programming and evicting keys must be done through vendor-specific SMC calls. To support this hardware, add a ->program_key() method to 'struct cqhci_host_ops'. This allows overriding the standard CQHCI crypto key programming / eviction procedure. This is inspired by the corresponding UFS crypto support, which uses these same SMC calls. See commit 1bc726e26ef3 ("scsi: ufs: Add program_key() variant op"). Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Satya Tangirala <satyat@google.com> Reviewed-and-tested-by: Peng Zhou <peng.zhou@mediatek.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210126001456.382989-6-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: cqhci: add support for inline encryptionEric Biggers
Add support for eMMC inline encryption using the blk-crypto framework (Documentation/block/inline-encryption.rst). eMMC inline encryption support is specified by the upcoming JEDEC eMMC v5.2 specification. It is only specified for the CQ interface, not the non-CQ interface. Although the eMMC v5.2 specification hasn't been officially released yet, the crypto support was already agreed on several years ago, and it was already implemented by at least two major hardware vendors. Lots of hardware in the field already supports and uses it, e.g. Snapdragon 630 to give one example. eMMC inline encryption support is very similar to the UFS inline encryption support which was standardized in the UFS v2.1 specification and was already upstreamed. The only major difference is that eMMC limits data unit numbers to 32 bits, unlike UFS's 64 bits. Like we did with UFS, make the crypto support opt-in by individual drivers; don't enable it automatically whenever the hardware declares crypto support. This is necessary because in every case we've seen, some extra vendor-specific logic is needed to use the crypto support. Co-developed-by: Satya Tangirala <satyat@google.com> Signed-off-by: Satya Tangirala <satyat@google.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Satya Tangirala <satyat@google.com> Reviewed-and-tested-by: Peng Zhou <peng.zhou@mediatek.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210125183810.198008-5-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: cqhci: initialize upper 64 bits of 128-bit task descriptorsEric Biggers
Move the task descriptor initialization into cqhci_prep_task_desc(). In addition, make it explicitly initialize all 128 bits of the task descriptor if the host controller is using 128-bit task descriptors, rather than relying on the implicit zeroing from dmam_alloc_coherent(). This is needed to prepare for CQHCI inline encryption support, which requires 128-bit task descriptors and uses the upper 64 bits. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Satya Tangirala <satyat@google.com> Reviewed-and-tested-by: Peng Zhou <peng.zhou@mediatek.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210126001456.382989-4-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: cqhci: rename cqhci.c to cqhci-core.cEric Biggers
Rename cqhci.c to cqhci-core.c so that another source file can be added to the cqhci module without having to rename the module. Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-and-tested-by: Peng Zhou <peng.zhou@mediatek.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210126001456.382989-3-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: core: Add basic support for inline encryptionEric Biggers
In preparation for adding CQHCI crypto engine (inline encryption) support, add the code required to make mmc_core and mmc_block aware of inline encryption. Specifically: - Add a capability flag MMC_CAP2_CRYPTO to struct mmc_host. Drivers will set this if the host and driver support inline encryption. - Embed a blk_keyslot_manager in struct mmc_host. Drivers will initialize this (as a device-managed resource) if the host and driver support inline encryption. mmc_block registers this keyslot manager with the request_queue of any MMC card attached to the host. - Make mmc_block copy the crypto keyslot and crypto data unit number from struct request to struct mmc_request, so that drivers will have access to them. - If the MMC host is reset, reprogram all the keyslots to ensure that the software state stays in sync with the hardware state. Co-developed-by: Satya Tangirala <satyat@google.com> Signed-off-by: Satya Tangirala <satyat@google.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Satya Tangirala <satyat@google.com> Reviewed-and-tested-by: Peng Zhou <peng.zhou@mediatek.com> Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20210126001456.382989-2-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01scsi: ufs: use devm_blk_ksm_init()Eric Biggers
Use the new resource-managed variant of blk_ksm_init() so that the UFS driver doesn't have to manually call blk_ksm_destroy(). Signed-off-by: Eric Biggers <ebiggers@google.com> Reviewed-by: Satya Tangirala <satyat@google.com> Link: https://lore.kernel.org/r/20210121082155.111333-3-ebiggers@kernel.org Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01block/keyslot-manager: introduce devm_blk_ksm_init()Eric Biggers
Add a resource-managed variant of blk_ksm_init() so that drivers don't have to worry about calling blk_ksm_destroy(). Note that the implementation uses a custom devres action to call blk_ksm_destroy() rather than switching the two allocations to be directly devres-managed, e.g. with devm_kmalloc(). This is because we need to keep zeroing the memory containing the keyslots when it is freed, and also because we want to continue using kvmalloc() (and there is no devm_kvmalloc()). Signed-off-by: Eric Biggers <ebiggers@google.com> Reviewed-by: Satya Tangirala <satyat@google.com> Acked-by: Jens Axboe <axboe@kernel.dk> Link: https://lore.kernel.org/r/20210121082155.111333-2-ebiggers@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-aspeed: Fix kunit-related build errorAndrew Jeffery
Randy found that with the following Kconfig settings we have duplicate definitions (e.g. __inittest()) in sdhci-of-aspeed due to competing module_init()/module_exit() calls from kunit and driver the itself. ``` CONFIG_MMC_SDHCI_OF_ASPEED=m CONFIG_MMC_SDHCI_OF_ASPEED_TEST=y ``` Conditionally open-code the kunit initialisation to avoid the error. Fixes: 7efa02a981d6 ("mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations") Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Link: https://lore.kernel.org/r/20210122114852.3790565-1-andrew@aj.id.au Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: remove sirf prima/atlas driverArnd Bergmann
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120142801.334550-3-arnd@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: remove dw_mmc-zx driverArnd Bergmann
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <jun.nie@linaro.org> Cc: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210120142801.334550-2-arnd@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: atmel-mci: Assign boolean values to a bool variableJiapeng Zhong
Fix the following coccicheck warnings: ./drivers/mmc/host/atmel-mci.c:2436:2-34: WARNING: Assignment of 0/1 to bool variable. ./drivers/mmc/host/atmel-mci.c:2425:2-20: WARNING: Assignment of 0/1 to bool variable. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Zhong <abaci-bugfix@linux.alibaba.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/1611128377-66216-1-git-send-email-abaci-bugfix@linux.alibaba.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-iproc: Add ACPI bindings for the RPiJeremy Linton
The RPi4 has an Arasan controller it carries over from the RPi3 and a newer eMMC2 controller. Because of a couple of quirks, it seems wiser to bind these controllers to the same driver that DT is using on this platform rather than the generic sdhci_acpi driver with PNP0D40. So, BCM2847 describes the older Arasan and BRCME88C describes the newer eMMC2. The older Arasan is reusing an existing ACPI _HID used by other OSes booting these tables on the RPi. With this change, Linux is capable of utilizing the SD card slot, and the Wi-Fi when booted with UEFI+ACPI on the RPi4. Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210120000406.1843400-2-jeremy.linton@arm.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: mmci: Convert bindings to DT schemaLinus Walleij
This converts the MMCI bindings from simple text to a proper schema. Cc: devicetree@vger.kernel.org Cc: Marek Vasut <marex@denx.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20210119100655.2755164-1-linus.walleij@linaro.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: test: clean up mmc_test_cleanup()Yue Hu
mmc_test_cleanup() has same body as __mmc_test_prepare() with write except the character to memset(). Signed-off-by: Yue Hu <huyue2@yulong.com> Link: https://lore.kernel.org/r/20210119073705.375-1-zbestahu@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: test: remove the shutdown functionYue Hu
Since it's doing nothing for shutdown behavior. And the callback will be checked firstly in mmc_bus_shutdown(). Signed-off-by: Yue Hu <huyue2@yulong.com> Link: https://lore.kernel.org/r/20210119051425.305-1-zbestahu@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: core: remove unused host parameter of mmc_sd_get_csd()Yue Hu
The host parameter is not used in the body of mmc_sd_get_csd(), so let's remove it. Update related code at the same time. Signed-off-by: Yue Hu <huyue2@yulong.com> Link: https://lore.kernel.org/r/20210118084520.241-1-zbestahu@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01MAINTAINERS: Add entry for the ASPEED SD/MMC driverAndrew Jeffery
Add myself as the maintainer. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210114031433.2388532-6-andrew@aj.id.au Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-aspeed: Add KUnit tests for phase calculationsAndrew Jeffery
Converting degrees of phase to logic delays is irritating to test on hardware, so lets exercise the function using KUnit. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210114031433.2388532-5-andrew@aj.id.au Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-aspeed: Add AST2600 bus clock supportAndrew Jeffery
The AST2600 can achieve HS200 speeds with a change to the bus clock divisor behaviour. The divisor can also be more accurate with respect to the requested clock rate, but keep the one-hot behaviour for backwards compatibility with the AST2400 and AST2500. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210114031433.2388532-4-andrew@aj.id.au Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-aspeed: Expose clock phase controlsAndrew Jeffery
The Aspeed SD/eMMC controllers expose configurable clock phase correction by inserting delays of up to 15 logic elements in length into the bus clock path. The hardware supports independent configuration for both bus directions on a per-slot basis. The timing delay per element encoded in the driver was experimentally determined by scope measurements. The phase controls for both slots are grouped together in a single register of the global register block of the SD/MMC controller(s), which drives the use of a locking scheme between the SDHCIs and the global register set. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210114031433.2388532-3-andrew@aj.id.au Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: core: Add helper for parsing clock phase propertiesAndrew Jeffery
Drivers for MMC hosts that accept phase corrections can take advantage of the helper by embedding an instance of struct mmc_clk_phase_map in their private data and invoking mmc_of_parse_clk_phase() to extract phase parameters. It is the responsibility of the host driver to translate and apply the extracted values to hardware as required. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210114031433.2388532-2-andrew@aj.id.au Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01dt-bindings: mmc: sdhci-am654: fix compatible for j7200Grygorii Strashko
On TI J7200 SoC the SDHCI controller compatible defined as "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit" or "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit" which causes dtbs_check warnings: mmc@4f80000: compatible: ['ti,j7200-sdhci-8bit', 'ti,j721e-sdhci-8bit'] is too long mmc@4f80000: compatible: Additional items are not allowed ('ti,j721e-sdhci-8bit' was unexpected) mmc@4fb0000: compatible:0: 'ti,j7200-sdhci-4bit' is not one of ['ti,am654-sdhci-5.1', 'ti,j721e-sdhci-8bit', 'ti,j721e-sdhci-4bit', 'ti,j7200-sdhci-8bit', 'ti,j721e-sdhci-4bit', 'ti,am64-sdhci-8bit', 'ti,am64-sdhci-4bit'] mmc@4fb0000: compatible: ['ti,j7200-sdhci-4bit', 'ti,j721e-sdhci-4bit'] is too long mmc@4fb0000: compatible: Additional items are not allowed ('ti,j721e-sdhci-4bit' was unexpected) Fix it by adding missing compatible strings and their combinations. Fixes: 407d0c2cdd12 ("dt-bindings: mmc: sdhci-am654: Convert sdhci-am654 controller documentation to json schema") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20210115193218.5809-1-grygorii.strashko@ti.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: omap_hsmmc: Simplify bool comparison and conversionYang Li
Fix the following coccicheck warning: ./drivers/mmc/host/omap_hsmmc.c:297:6-25: WARNING: Comparison of 0/1 to bool variable According to the context, vqmmc_enabled is more suitable for bool type. Reported-by: Abaci Robot<abaci@linux.alibaba.com> Signed-off-by: Yang Li <abaci-bugfix@linux.alibaba.com> Link: https://lore.kernel.org/r/1610704281-11036-1-git-send-email-abaci-bugfix@linux.alibaba.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: core: convert comma to semicolonZheng Yongjun
Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com> Link: https://lore.kernel.org/r/20201216131737.14883-1-zhengyongjun3@huawei.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-pci-gli: Finetune HS400 RX delay for GL9763ERenius Chen
To improve the compatibility of GL9763E with HS400 eMMC cards, finetune the RX delay of HS400 mode. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Link: https://lore.kernel.org/r/20210111082249.17092-1-reniuschengl@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-arasan: Use dev_err_probe() to avoid spamming logsMuhammad Husaini Zulkifli
Using dev_err_probe() can avoid spamming logs when probe is deferred. This function can also help to reduce code the size, uniform error handling and simplify the code. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-5-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-arasan: Add structure device pointer in probe functionMuhammad Husaini Zulkifli
Add struct device *dev in probe func() so that it can widely use in probe to make code more readable. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-4-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-arasan: Convert to use np instead of pdev->dev.of_nodeMuhammad Husaini Zulkifli
Use np pointer to simplify code and improve readability. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-3-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-of-arasan: use of_device_get_match_data()Muhammad Husaini Zulkifli
Use of_device_get_match_data() helper to get the match-data. Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com> Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Andy Shevchenko <andriy.shevchenko@intel.com> Link: https://lore.kernel.org/r/20210114152700.21916-2-muhammad.husaini.zulkifli@intel.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL9763ERenius Chen
GL9763E enters ASPM L1 state after a very short idle in default, even during a burst of request. So the R/W performance of GL9763E is low with some platforms, which support ASPM mechanism, due to entering ASPM L1 state very frequently in R/W process. Set the L1 entry delay bits in vendor-specific register to 0x3FF to enlarge the idle period to 260us for improving the R/W performance of GL9763E. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Link: https://lore.kernel.org/r/20210115054736.27769-1-reniuschengl@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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