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2016-02-25ARM64: zynqmp: Keep gpio node alphabetically sortedMichal Simek
No functional change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-24Merge tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson
next/dt64 mvebu dt64 for 4.6 (part 1) Device tree part of the Armada 3700 support: - binding for the Armada 3700 SoCs - device tree files for the SoCs and a board - tidy up the Marvell related files * tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu: arm64: dts: add the Marvell Armada 3700 family and a development board devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family Documentation: dt: Tidy up the Marvell related files Documentation: dt-bindings: Add a new compatible for the Armada 3700 Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24arm64: dts: amd: Fix-up for ccn504 and kcs nodesSuravee Suthikulpanit
This is a fix-up patch based on the review comment from Arnd regarding: * fix ccn504 address in the node name * remove kcs interrupt-name Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24Merge tag 'v4.6-rockchip-dts64-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 Define the tuning-related mmc clocks and move from gpio-key,wakeup to the more generic wakeup-source property. * tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source property arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24arm64: dts: qcom: msm8916: Add RPMCC DT nodeGeorgi Djakov
Add the RPM Clock Controller DT node and include the necessary header file for clocks. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24ARM64: dts: qcom: Remove size elements from pmic reg propertiesStephen Boyd
The #size-cells for the pmics are 0, but we specify a size in the reg property so that MPP and GPIO modules can figure out how many pins there are. Now that we've done that by counting irqs, we can remove the size elements in the reg properties and be DT compliant. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: msm8996: Add #power-domain-cells propertyRajendra Nayak
Add #power-domain-cells property for both the gcc and mmcc clock controller nodes as they both supports power domains (gdsc's) Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: apq8016-sbc: Add real regulators and pinctrl for sdhcSrinivas Kandagatla
This patch adds real regulators and pinctrl nodes for sdhc_1. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: apq8016-sbc: move sdhci node under soc nodeSrinivas Kandagatla
To be consistent with other nodes move sdhci node under the soc node, rather than using lable references. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: apq8016-sbc: make 1.8v available on LS expansionSrinivas Kandagatla
96boards mezzanine boards on LS expansion require 1.8v as per 96boards specifications, so enable the corresponding regulators and make them always-on. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: apq8016-sbc: add regulators supportSrinivas Kandagatla
This patch adds required regulators for apq8016-sbc aka db410c board. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: qcom: add lable for smd rpm regulatorsSrinivas Kandagatla
This patch adds label to smd rpm regulators so that the board level file can use the label directly to populate the regulators, rather than having deep nesting. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: remove s2 regulator from smd regulators.Srinivas Kandagatla
s2 is spmi controller regulator on msm8916 according to downstream 3.10 kernel, so remove it from the dt to avoid confusion an use of it. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: qcom: add correct drive strenght on cs pinsSrinivas Kandagatla
2mA drive strenght is not enough to drive chipselect low on hardware configurations with level shifters, 16mA should give good range to allow such configurations to work. This issue was noticed while testing spi on db410c with sensor board. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: qcom: remove redundant spi cs pins from pinconfSrinivas Kandagatla
This patch removes redundant pins from spi pinconf as these are already specified in pinconf_cs. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: apq8016-sbc: Add aliases to spi device.Srinivas Kandagatla
This patch adds aliases to spi device so that it can get proper bus number rather than a random number. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: Add L2 cache node to msm8916Stephen Boyd
The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the dtsi file so that the cache hierarchy can be probed. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: Rename qcom,gcc node to clock-controllerStephen Boyd
Use the standard name for clock controller nodes instead of a qcom specific name. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24arm64: dts: qcom: Add pm8994 gpios and MPPsStephen Boyd
Add the gpio and MPP devices to the pm8994 pmic dts. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-23arm64: dts: qcom: Add pm8994, pmi8994, pm8004 PMIC skeletonsStephen Boyd
Add the skeleton nodes for the PMICs found on msm8996-mtp devices. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-23arm64: dts: Add msm8996 SoC and MTP board supportStephen Boyd
Add initial device tree support for the Qualcomm MSM8996 SoC and MTP8996 evaluation board. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-20dt-bindings: Add documentation for Broadcom VulcanJayachandran C
Update arm/cpus.txt to add "brcm,vulcan" CPU. Add documentation for Broadcom Vulcan boards in arm/bcm/brcm,vulcan-soc.txt Signed-off-by: Jayachandran C <jchandra@broadcom.com>
2016-02-19ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issueEddie Huang
MT8173 E1 chip has one bug that if turn off USB power domain, vcore power will also be off, thus cause modules using vcore power domain fail, like MMC. The E1 chip only found on MT8173-evb board and this board only has E1 chip, so implement this as a board specific workaround. Pwrapper use vcore power, so add pwrapper using USB power domain to keep USB power domain not to zero and disabled. Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19arm64: dts: r8a7795: Add GIC-400 virtual interfacesDirk Behme
Besides the distributor and the CPU interface the GIC-400 additionally supports the virtual interface control blocks and the virtual CPU interfaces. Add the physical base addresses and size for these. See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0471b/index.html -> 3.2. GIC-400 register map and Linux kernel's Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for more details. For the at GICH Virtual interface control blocks at 0xf1040000 cover the whole 128kB (0x20000) range. This is done based on the advice from Marc Zyngier http://www.spinics.net/lists/arm-kernel/msg483139.html Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-17arm64: dts: add the Marvell Armada 3700 family and a development boardGregory CLEMENT
Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53 CPUs. There are two members in this family: the Armada 3710 (Single CPU) and the Armada 3720 (Dual CPUs). It also adds a dts file for the Marvell Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-17devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC familyGregory CLEMENT
The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit introduces the Device Tree binding that documents the top-level compatible strings for Armada 3700 based platforms. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
2016-02-17Documentation: dt: Tidy up the Marvell related filesGregory CLEMENT
Over the last releases we have added more and more Marvell related binding directly in the arm directory. It's time to have our proper directory inside it, and move all the files in it. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
2016-02-17Documentation: dt-bindings: Add a new compatible for the Armada 3700Gregory CLEMENT
The AHCI interfaces used in the Armada 3700 has a few differences with the one used in the Armada 38x, so it deserves its own compatible string. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
2016-02-17arm64: dts: r8a7795: Add INTC-EX device nodeMagnus Damm
Add a single r8a7795 INTC-EX device node to support external IRQ pins IRQ0 -> IRQ5. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-17arm64: dts: r8a7795: Add CA53 L2 cache-controller nodeGeert Uytterhoeven
Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-17arm64: dts: r8a7795: Add missing properties to CA57 L2 cache nodeGeert Uytterhoeven
Add the missing "cache-unified" and "cache-level" properties to the Cortex-A57 cache-controller node. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-16arm64: dts: r8a7795: use GIC_* definesSimon Horman
Use GIC_* defines for GIC interrupt cells in r8a7795 device tree. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-14arm64: dts: ls1043a: Add quirk for Erratum A009116Rajesh Bhagat
Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-14arm64: dts: ls2080a: Add quirk for Erratum A009116Lijun Pan
Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-02-12arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2Ray Jui
This patch enables PCIe0 and PCIe4 for NS2 by adding appropriate DT nodes in NS2 DT. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12arm64: dts: Add ARM SP805 watchdog DT node for NS2Anup Patel
We have one ARM SP805 watchdog instance on NS2 for non-secure software hence this patch adds appropriate watchdog DT node in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Pramod KUMAR <pramodku@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12dt-bindings: watchdog: Add ARM SP805 DT bindingsAnup Patel
The ARM SP805 DT node is already present in various DTS files. This patch adds missing DT bindings documentation for ARM SP805. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Vikram Prakash <vikramp@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12arm64: dts: Add ARM SP804 timer DT nodes for NS2Anup Patel
We have four ARM SP804 dual-mode timer instances in NS2 SoC hence this patch adds appropriate DT nodes for NS2. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Pramod KUMAR <pramodku@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12arm64: dts: Add SDHCI DT node for NS2Anup Patel
The IPROC SDHCI driver works fine for SDIO 3.0 on NS2 so let's enable it for NS2 SoC in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Vikram Prakash <vikramp@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-11dts: arm64: Add EFUSE device nodeandrew-ct.chen@mediatek.com
Add Mediatek MT8173 EFUSE device node Signed-off-by: Andrew-CT Chen <andrew-ct.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-11arm64: dts: mt8173: Add nor flash nodeBayi Cheng
Add Mediatek nor flash node Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium. org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-10arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source propertySudeep Holla
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source. Few dts files assign value "1" to gpio-key,wakeup and in one instance a value "0" is assigned probably assuming it won't be enabled as a wakeup source. Since the presence of the boolean property indicates it is enabled, value of "0" have no value. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property which inturn fixes the above mentioned issue. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-08Merge tag 'renesas-arm64-dt-for-v4.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Renesas ARM64 Based SoC DT Updates for v4.6 * Use SCIF fallback compatibility strings * Add Baud Rate Generator (BRG) support for (H)SCIF * Enable SCIF_CLK frequency and pins * Enable USB 3.0 host * Add Add USB-DMAC device nodes * Complete SYS-DMAC device nodes * tag 'renesas-arm64-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: salvator-x: Enable SCIF_CLK frequency and pins arm64: dts: r8a7795: Add BRG support for (H)SCIF arm64: dts: r8a7795: Rename the serial port clock to fck arm64: dts: r8a7795: Add SCIF fallback compatibility strings arm64: dts: r8a7795: Add USB-DMAC device nodes arm64: dts: salvator-x: enable usb3.0 host channel 0 arm64: dts: r8a7795: Add USB3.0 host device nodes arm64: dts: r8a7795: Complete SYS-DMAC nodes Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add support for AMD/Linaro 96Boards Enterprise Edition Server boardSuravee Suthikulpanit
Add device tree file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board. This is based on the AMD Seattle Rev.B0 system Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add support for new AMD Overdrive boardsSuravee Suthikulpanit
Add device tree files for AMD Overdrive boards which comes with AMD Seattle Revision B0 and B1 SOCs. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add AMD XGBE device tree fileTom Lendacky
Add AMD XGBE device tree file, which is available in AMD Seattle RevB. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add KCS device tree nodeBrijesh Singh
Add KCS device node to support IPMI solution on Overdrive system. Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add PERF CCN-504 device tree nodeSuravee Suthikulpanit
Add PERF CCN-504 device tree node. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Misc changes for GPIO devicesSuravee Suthikulpanit
Add new GPIO device nodes and fix clock on gpio0. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Misc changes for SATA device tree nodesSuravee Suthikulpanit
Add new SATA1 device node, and fix the register range size of SATA0. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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