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2019-01-25drm/amdgpu: set the executable flag on unused Vega10 PTEs v2Christian König
Otherwise we run into a non-retry fault on access. It seems to be a hardware bug that the executable bit has higher priority than the valid bit. v2: handle clears as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/ttm: stop always moving BOs on the LRU on page faultChristian König
Move the BO on the LRU only when it is actually moved by a DMA operation. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-And-Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support retrieving and adjusting dcefclock power levels V2Evan Quan
User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support retrieving and adjusting fclock power levels V2Evan Quan
User can use "pp_dpm_fclk" to retrieve and adjust fclock power levels. V2: expose this interface for Vega20 and later ASICs only Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support retrieving and adjusting SOC clock power levels V2Evan Quan
User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/powerplay: support enabled ppfeatures retrieving and setting V3Evan Quan
User can use "ppfeatures" sysfs interface to retrieve and set enabled powerplay features. V2: expose this feature for Vega10 and later dGPUs V3: squash in removal of unused variable (Alex) Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: set bulk_moveable to false when lru changed v2Chunming Zhou
if lru is changed, we cannot do bulk moving. v2: root bo isn't in bulk moving, skip its change. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/ttm: add lru notify to bo driver v2Chunming Zhou
allow driver do somethings when lru changed. v2: address Michel's comments. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu/psp: ignore psp response statusAaron Liu
In some cases, psp response status is not 0 even there is no problem while the command is submitted. Some version of PSP FW doesn't write 0 to that field. So here we would like to only print a warning instead of an error during psp initialization to avoid breaking hw_init and it doesn't return -EINVAL. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Xiangliang Yu<Xiangliang.Yu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Paul Menzel <pmenzel+amd-gfx@molgen.mpg.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: Setting doorbell range registers earlierOak Zeng
HW doorbell writing routing policy: writing to doorbell not in SDMA/IH/MM/ACV doorbell range will be routed to CP. So CP doorbell routing depends on doorbell range setting of above blocks. Setting doorbell range of above blocks earlier (soc15_common_hw_init) to make sure CP doorbell writing be routed to CP block. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: Fix sdma doorbell range settingOak Zeng
Different ASIC has different SDMA queue number so different SDMA doorbell range. Introduce an extra parameter to sdma_doorbell_range function and set sdma doorbell range correctly. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: Add per device sdma_doorbell_range fieldOak Zeng
Different ASIC has different sdma doorbell range. Add a per device sdma_doorbell_range field and initialize it. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu/soc15: return proper error codes in baco resetAlex Deucher
Rather than just -1. Reviewed-by: JimQu <Jim.Qu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Include names of all PP clock typesRafał Miłecki
This fixes printing clock names in cases like: [ 5.352311] [drm] DM_PPLIB: values for Invalid clock [ 5.352313] [drm] DM_PPLIB: 400000 in kHz [ 5.352313] [drm] DM_PPLIB: 933000 in kHz [ 5.352314] [drm] DM_PPLIB: 1067000 in kHz [ 5.352315] [drm] DM_PPLIB: 1200000 in kHz [ 5.352317] [drm] DM_PPLIB: values for Invalid clock [ 5.352318] [drm] DM_PPLIB: 300000 in kHz [ 5.352318] [drm] DM_PPLIB: 600000 in kHz [ 5.352319] [drm] DM_PPLIB: 626000 in kHz [ 5.352320] [drm] DM_PPLIB: 654000 in kHz (source: HP EliteBook 745 G5 w. RAVEN 0x1002:0x15DD 0x103C:0x83D5 0xD1) On my system above "Invalid" names got replaced by "F" and "DCF". The same problem was occurring on Huawei Matebook D with just 667000 kHz instead of 400000 kHz. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd: fix typoMatteo Croce
Fix spelling mistake: "lenght" -> "length" Signed-off-by: Matteo Croce <mcroce@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amd/display: Skip create new stream if crtc state doesn't changeJerry (Fangzhi) Zuo
Need to check if crtc state is changed so that mode set is required before trying to create new stream. It deals with the MST hotplug use case when plug back to the same connector where the failure to create new stream for the inactive crtc on the old connector. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: use BACO reset on vega20 if platform supportJim Qu
Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: use BACO reset if platform support (v2)Jim Qu
It will fall back to use mode1 reset if platform does not support BACO feature. v2: squash in warning fix (Alex) Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu/powerper: add vega20 BACO functionsJim Qu
Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: update THM IP register header to support BACOJim Qu
Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: also include NBIO v7.4 register mask headerJim Qu
Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: update NBIO v7.4 to support BACOJim Qu
Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: expose BACO interfaces to upper level from PPJim Qu
Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdgpu: add BACO interfaces for vega10Jim Qu
V2: delay 20ms before BACO out. V3: rename function to vega10_baco_xxx Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-25drm/amdpgu: add common functions for BACO feature in PP (v2)Jim Qu
V2: squash in crash fix for non-register commands (Alex) Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-24drm/i915: Update DRIVER_DATE to 20190124Rodrigo Vivi
Signed-off-by: Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com>
2019-01-24Merge tag 'gvt-next-2019-01-24' of https://github.com/intel/gvt-linux into ↵Rodrigo Vivi
drm-intel-next-queued gvt-next-2019-01-24 - split kvmgt as seperate module (Zhenyu) - Coffeelake GVT support (Fred) - const treatment and change for kernel type (Jani) Signed-off-by: Rodrigo Vivi <vivijim@rdvivi-cozumel.jf.intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190124054048.GO7203@zhen-hp.sh.intel.com
2019-01-24drm/i915: Make HW readout mark CRTC scaler as in use.Maarten Lankhorst
This way we don't accidentally double allocate it. Noticed this when I wrote a patch to sanity check all of the scaler state. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190108160842.13396-4-maarten.lankhorst@linux.intel.com
2019-01-24drm/i915: Enable fastset for non-boot modesets.Maarten Lankhorst
Now that our state comparison functions are pretty complete, we should enable fastset by default when a modeset can be avoided. Even if we're not completely certain about the inherited state, we can be certain after the first modeset that our sw state matches the hw state. There is one testcase explicitly testing fastset, kms_panel_fitting.atomic-fastset but other testcases do so indirectly because most tests don't clean up the display during exit, or otherwise indirectly preserve mode by doing igt_display_reset or inheriting during init. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Hans de Goede <hdegoede@redhat.com> [mlankhorst: Use DRM_DEBUG_KMS. (j4ni)] Link: https://patchwork.freedesktop.org/patch/msgid/20190108160842.13396-3-maarten.lankhorst@linux.intel.com
2019-01-24drm/i915/backlight: Fix backlight takeover on LPT, v3.Maarten Lankhorst
On lynxpoint the bios sometimes sets up the backlight using the CPU display, but the driver expects using the PWM PCH override register. Read the value from the CPU register, then convert it to the other units by converting from the old duty cycle, to freq, to the new units. This value is then programmed in the override register, after which we set the override and disable the CPU display control. This allows us to switch the source without flickering, and make the backlight controls work in the driver. Changes since v1: - Read BLC_PWM_CPU_CTL2 to cpu_ctl2. - Clean up cpu_mode if slightly. - Always disable BLM_PWM_ENABLE in cpu_ctl2. Changes since v2: - Simplify cpu_mode handling (Jani) Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108225 Cc: Basil Eric Rabi <ericbasil.rabi@gmail.com> Cc: Hans de Goede <jwrdegoede@fedoraproject.org> Cc: Tolga Cakir <cevelnet@gmail.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Tolga Cakir <cevelnet@gmail.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190108160842.13396-2-maarten.lankhorst@linux.intel.com
2019-01-24drm/i915/backlight: Restore backlight on resume, v3.Maarten Lankhorst
Restore our saved values for backlight. This way even with fastset on S4 resume we will correctly restore the backlight to the active values. Changes since v1: - Call enable_backlight() when backlight.level is set. On suspend backlight.enabled is always cleared, this makes it not a good indicator. Also check for crtc->state->active. Changes since v2: - Use the new update_pipe() callback to run this on resume as well. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Tolga Cakir <cevelnet@gmail.com> Cc: Basil Eric Rabi <ericbasil.rabi@gmail.com> Cc: Hans de Goede <jwrdegoede@fedoraproject.org> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190108160842.13396-1-maarten.lankhorst@linux.intel.com
2019-01-24Merge tag 'drm-misc-next-2019-01-23' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.1: UAPI Changes: - Addition of the Allwinner tiled format modifier Cross-subsystem Changes: Core Changes: - dma-buf documentation improvements - Removal of now unused fbdev helpers - Addition of new drm fbdev helpers - Improvements to tinydrm - Addition of new drm_fourcc helpers - Impromevents to i2c-over-aux to handle I2C_M_STOP Driver Changes: - Add support for the TI DS90C185 LVDS bridge - Improvements to the thc63lvdm83d bridge - Improvements to sun4i YUV and scaler support - Fix to the powerdown sequence of panel-innolux Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190123110317.h4tovujaydo2bfz2@flea
2019-01-24drm/i915: De-inline intel_context_init()Chris Wilson
Nip some inline spaghetti in the bud before the problem gets too bad. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190124083710.7033-1-chris@chris-wilson.co.uk
2019-01-24Merge tag 'drm-intel-next-2019-01-10' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next - Unwind failure on pinning the gen7 PPGTT (Chris) - Fastset updates to make sure DRRS and PSR are properly enabled (Hans) - Header include clean-up (Brajeswar, Jani) - Improvements and clean-up on debugfs (Chris, Jani) - Avoid division by zero on CNL clocks setup (Xiao) - Restrict PSMI context load w/a to Haswell GT1 (Chris) - Remove HW semaphores for gen7 inter-engine sync (Chris) - Pull the render flush into breadcrumb emission (Chris) - i915_params copy and free helpers and other reorgs and docs (Jani) - Remove has_pooled_eu static initializer (Tvrtko) - Updates on kerneldoc (Chris) - Remove redundant trailing request flush (Chris) - ringbuffer irq seqno fixes and clean-up (Chris) - splitting off runtime device info and other clean-up around (Jani) - Selftests improvements (Chris, Daniele) - Flush RING_IMR changes before changing the global GT IMR on gen6 and HSW (Chris) - Some improvements and fixes around GPU reset and GPU hang report (Chris) - Remove partial attempt to swizzle on pread/pwrite (Chris) - Return immediately if trylock fails for direct-reclaim (Chris) - Downgrade scare message for unknown HuC firmware (Jani) - ACPI / PMIC for MIPI / DSI (Hans) - Reduce i915_request_alloc retirement to local context (Chris) - Init per-engine WAs for all engines (Daniele) - drop DPF code for gen8+ (Daniele) - Guard error capture against unpinned vma (Chris) - Use mutex_lock_killable from inside the shrinker (Chris) - Removing pooling from struct_mutex from vmap shrinker (Chris) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Fri 11 Jan 2019 09:58:18 AEST # gpg: using RSA key FA625F640EEB13CA # gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" # gpg: aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C E2A3 FA62 5F64 0EEB 13CA # Conflicts: # drivers/gpu/drm/i915/intel_dp.c # drivers/gpu/drm/i915/intel_drv.h From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190114183820.GA2855@intel.com
2019-01-24drm/i915/crt: simplify CRT VBT check on pre-VLV/DDIJani Nikula
The VBT int_crt_support can't be trusted on earlier platforms, and is always set to true in intel_bios.c for pre-DDI and pre-VLV platforms. We can simplify the output setup by unconditionally calling intel_crt_init() for these platforms. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122082307.4003-7-jani.nikula@intel.com
2019-01-24drm/i915/lvds: simplify gen 2 lvds presenceJani Nikula
Gen 2 mobile and not I830 is, in fact, I85X. Simplify. Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122082307.4003-6-jani.nikula@intel.com
2019-01-24drm/i915: rename has_edp_a() to ilk_has_edp_a()Jani Nikula
Clarify that the name is specific to ILK+ PCH platforms. v2: prefix the name with ilk rather than pch (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122082307.4003-5-jani.nikula@intel.com
2019-01-24drm/i915/tv: only call intel_tv_init() on platforms that might have TVJani Nikula
With most platforms not having TV support, only call intel_tv_init() on platforms that might actually have TV, specifically gens 3 and 4. This puts intel_tv_init() more in line with the rest of the outputs, and makes it slightly easier for the uninitiated to figure out which platforms actually have what. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122082307.4003-4-jani.nikula@intel.com
2019-01-24drm/i915/lvds: nuke intel_lvds_supported()Jani Nikula
Now that intel_lvds_init() is only called for platforms that might have LVDS, move the remaining checks to intel_setup_outputs(), again similar to other outputs, and remove the overlapping checks. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122082307.4003-3-jani.nikula@intel.com
2019-01-24drm/i915/lvds: only call intel_lvds_init() on platforms that might have LVDSJani Nikula
With new platforms not having LVDS support, only call intel_lvds_init() on platforms that might actually have LVDS. Move the comment about eDP init to the PCH block where it's relevant. This puts intel_lvds_init() more in line with the rest of the outputs, and makes it slightly easier for the uninitiated to figure out which platforms actually have what. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122082307.4003-2-jani.nikula@intel.com
2019-01-24drm/i915/crt: split out intel_crt_present() to platform specific setupJani Nikula
With new platforms not having CRT support and most conditions in intel_crt_present() being specific to DDI, split out the CRT initialization to platform specific blocks in the if ladder. Add new Pineview block for this. This puts intel_crt_init() more in line with the rest of the outputs, and makes it slightly easier for the uninitiated to figure out which platforms actually have what. v2: keep gen >= 9 check in intel_ddi_crt_present() (Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190122082307.4003-1-jani.nikula@intel.com
2019-01-23drm/i915: Validate userspace-provided color management LUT's (v4)Matt Roper
We currently program userspace-provided gamma and degamma LUT's into our hardware without really checking to see whether they satisfy our hardware's rules. We should try to catch tables that are invalid for our hardware early and reject the atomic transaction. All of our platforms that accept a degamma LUT expect that the entries in the LUT are always flat or increasing, never decreasing. Also, our GLK and ICL platforms only accept degamma tables with r=g=b entries; so we should also add the relevant checks for that in anticipation of degamma support landing for those platforms. v2: - Use new API (single check function with bitmask of tests to apply) - Call helper for our gamma table as well (with no additional tests specified) so that the table size will be validated. v3: - Don't call on the gamma table since the LUT size is already tested at property blob upload and we don't have any additional hardware constraints for that LUT. v4: - Apply equal color channel check on gen10 as well; the bspec has some strange tagging for CNL platforms, but this appears to apply there as well. (Ville) Cc: Uma Shankar <uma.shankar@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181218175158.5739-1-matthew.d.roper@intel.com
2019-01-23drm: Add color management LUT validation helper (v4)Matt Roper
Some hardware may place additional restrictions on the gamma/degamma curves described by our LUT properties. E.g., that a gamma curve never decreases or that the red/green/blue channels of a LUT's entries must be equal. Let's add a helper function that drivers can use to test that a userspace-provided LUT is valid and doesn't violate hardware requirements. v2: - Combine into a single helper that just takes a bitmask of the tests to apply. (Brian Starkey) - Add additional check (always performed) that LUT property blob size is always a multiple of the LUT entry size. (stolen from ARM driver) v3: - Drop the LUT size check again since drm_atomic_replace_property_blob_from_id() already covers this for us. (Alexandru Gheorghe) v4: - Use an enum to describe possible test values rather than #define's; this is cleaner to provide kerneldoc for. (Daniel Vetter) - s/DRM_COLOR_LUT_INCREASING/DRM_COLOR_LUT_NON_DECREASING/. (Ville) Cc: Uma Shankar <uma.shankar@intel.com> Cc: Swati Sharma <swati2.sharma@intel.com> Cc: Brian Starkey <Brian.Starkey@arm.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Brian Starkey <brian.starkey@arm.com> Reviewed-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20181217224415.12848-1-matthew.d.roper@intel.com
2019-01-23drm/i915/execlists: Mark up priority boost on preemptionChris Wilson
Record the priority boost we giving to the preempted client or else we may end up in a situation where the priority queue no longer matches the request priority order and so we can end up in an infinite loop of preempting the same pair of requests. Fixes: e9eaf82d97a2 ("drm/i915: Priority boost for waiting clients") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190123135155.21562-1-chris@chris-wilson.co.uk
2019-01-23drm/i915/icl: Adding few more device IDs for Ice LakeRodrigo Vivi
We just got aware that there was more IDs available at spec, so let's add them already. Cc: James Ausmus <james.ausmus@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190118055943.10252-1-rodrigo.vivi@intel.com
2019-01-23drm/i915/icl: do a posting read after irq installDaniele Ceraolo Spurio
When reading GEN11_GT_INTR_DWx closely after enabling the interrupts in gen11_irq_postinstall, the returned value is garbage. This can cause other parts of the setup code (e.g. gen11_reset_one_iir) to think that there are interrupts to be cleared when there are none. The garbage value is only seen on the first read done after the enable, so this looks like a posting issue. Adding a posting read after enabling the interrupts does indeed fix the problem. Note that the posting read has been purposely added outside of gen11_master_intr_enable since the issue has only been observed when the full interrupt setup is performed. Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190123023227.8117-1-daniele.ceraolospurio@intel.com
2019-01-23drm/i915/sdvo: switch to kernel typesJani Nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' v2: rebase Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190118120125.15484-1-jani.nikula@intel.com
2019-01-23drm/i915/gvt: switch to kernel typesJani Nikula
Mixed C99 and kernel types use is getting ugly. Prefer kernel types. sed -i 's/\buint\(8\|16\|32\|64\)_t\b/u\1/g' Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2019-01-22drm/i915/debugfs: Print PSR selective update status register valuesJosé Roberto de Souza
The value of this registers will be used to test if PSR2 is doing selective update and if the number of blocks match with the expected. v2: - Using new macros - Changed the string output v3: - reading PSR2_SU_STATUS registers together(Dhinakaran) - printing SU blocks of frames with 0 updates(Dhinakaran) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190117205548.28378-4-jose.souza@intel.com
2019-01-22drm/i915: Add PSR2 selective update status registers and bits definitionsJosé Roberto de Souza
This register contains how many blocks was sent in the past selective updates. Those registers are not kept set all the times but polling it after flip can show the values corresponding to the last 8 frames. v2: Improved macros(Dhinakaran) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190117205548.28378-3-jose.souza@intel.com
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 19:37:37 +0000