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2016-03-14drm/nouveau/fifo/gk104: read device topology information from hwBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: cosmetic engine->runlist changesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: don't attempt recovery of unknown mmu enginesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: identify fault-recovery members more clearlyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: rename spoon to pbdma, and move detection to oneinitBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: fix certain engines not being recovered after a faultBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: don't attempt recovery of unknown mmu enginesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: identify fault-recovery members more clearlyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: rename spooon to pbdma, and move detection to oneinitBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/fuc: Store $r0 in interrupt handlerRoy Spliet
It's supposed to always be 0, but at least nv_iowr() temporarily violates this. Since the ih touches $r0, it should be stored. Signed-off-by: Roy Spliet <rs855@cam.ac.uk> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: use imm32 in ld/st macrosKarol Herbst
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: use the call macro instead of using the call ↵Karol Herbst
instruction directly the macro deals with target specific differences and so we should always use this Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: replace mov+sethi with imm32Karol Herbst
on gk208+ we can simply mov 32bits, so we should have a single mov there v2: use or operator instead of add Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/pmu/fuc: fix imm32 for gk208+Karol Herbst
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: use vzalloc for allocating ramhtIlia Mirkin
Most calls to nvkm_ramht_new use 0x8000 as the size. This results in a fairly sizeable chunk of memory to be allocated, which may not be available with kzalloc. Since this is done fairly rarely (once per channel), use vzalloc instead. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: kick channel upon removalAlexandre Courbot
A channel may still be processed by the PBDMA even after removal, unless it is properly kicked. Some chips are more sensible to this than others, with GM20B triggering the issue very easily (the PBDMA will try to fetch methods from the previously-removed channel after a new one is added). Make sure this cannot happen by kicking the channel right after it is disabled, and before the new runlist is submitted. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/instmem/gk20a: add write barrier when releasing DMA objectAlexandre Courbot
When using the DMA-API for instmem, we may obtain a write-combined mapping. For such cases, add a write barrier in gk20a_instobj_release_dma() to make sure that all writes have reached memory at this time. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/device/pci: set as non-CPU-coherent on ARM64Alexandre Courbot
Without this buffer inconsistencies may appear between the CPU and GPU when using a PCI GPU on an ARM64 board. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/hwmon: fix crash on non-PCI platformsAlexandre Courbot
Registration of the hwmon device will fail on non-PCI systems since dev->pdev is NULL in that case. Use the more generic drm_device::dev member that points to the same and is always set no matter the platform. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau: silence unimportant HDMI status messageAlexandre Courbot
On non-PCI devices, nobody should really care if the device does not provide HDMI... Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/bo: consider DMA buffers on x86 onlyAlexandre Courbot
The DMA API has different semantics on different architectures. Currently on arm64, it can only provide memory from a small pool which dries up quickly if we attempt to allocate big buffers from it. Do not consider that option when running on non-x86, since regular TTM buffers are the (current) best-fit for ARM platforms. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/ltc/gf100: use more reasonable timeout valueAlexandre Courbot
LTC operations timeout was set to 2ms, which may be too low for devices that run at very low clocks (e.g. GM20B) and trigger timeout messages. Set the timeout to the default 2s. Also remove the redundant error messages since nvkm_wait_msec() will already display a warning. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: take runlist target into accountAlexandre Courbot
Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gf100: take runlist target into accountAlexandre Courbot
Bits 28:29 of RUNLIST_BASE specify the memory target of the runlist. Set it to 0x3 (SYS_MEM_NONCOHERENT) if the runlist object resides in system memory. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/fifo/gk104: fix chid bit maskXia Yang
Fix the channel id bit mask in FIFO schedule timeout error handling. FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff. Signed-off-by: Xia Yang <xiay@nvidia.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/instmem/gk20a: set DMA mask earlyAlexandre Courbot
DMA mask is typically set in nouveau_ttm_init(), but this function is called late during initialization and GK20A's instmem will have called DMA functions before this happens. Having a wrongly set DMA mask can result in the use of unneeded bounce buffers. Set it early to avoid this. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm206: remove implementation, it's now identical to gm200Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_nonctx from firmwareBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_method_init from firmwareBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_bundle_init from firmwareBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: switch over to using sw_ctx from firmwareBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/bios/extdev: also parse v4.1 tableKarol Herbst
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/hwmon: don't require therm to be valid to get any dataKarol Herbst
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/hwmon: add power consumptionKarol Herbst
v2: expose only if the sensor reading is valid Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/iccsense: implement for ina209, ina219 and ina3221Karol Herbst
based on Martins initial work v3: fix ina2x9 calculations v4: don't kmalloc(0), fix the lsb/pga stuff v5: add a field to tell if the power reading may be invalid add nkvm_iccsense_read_all function check for the device on the i2c bus Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/nvbios/iccsense: add parsing of the SENSE tableMartin Peres
Karol Herbst: v4: don't kmalloc(0) v5: stricter validation Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/subdev/iccsense: add new subdev for power sensorsMartin Peres
Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
2016-03-14drm/nouveau/secboot/gm20b: add secure boot supportAlexandre Courbot
Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/secboot/gm200: add secure-boot supportAlexandre Courbot
Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: do not load firmware for secure falconsAlexandre Courbot
Secure falcons' firmware is managed by secboot. Do not load it in GR for them. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gf100: add support for securely-managed falconsAlexandre Courbot
Start securely-managed falcons using secboot functions since the process for them is different from just writing CPUCTL. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add support for secure bootAlexandre Courbot
On GM200 and later GPUs, firmware for some essential falcons (notably GR ones) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to be able to access privileged registers, in a process known as Secure Boot. Secure Boot requires building a binary blob containing the firmwares and signatures of the falcons to be loaded. This blob is then given to a high-secure falcon running a signed loader firmware that copies the blob into a write-protected region, checks that the signatures are valid, and finally loads the verified firmware into the managed falcons and switches them to privileged mode. This patch adds infrastructure code to support this process on chips that require it. v2: - The IRQ mask of the PMU falcon was left - replace it with the proper irq_mask variable. - The falcon reset procedure expecting a falcon in an initialized state, which was accidentally provided by the PMU subdev. Make sure that secboot can manage the falcon on its own. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: load external firmware and bundlesAlexandre Courbot
Load firmware and bundles in GM200's constructor. The previously called GF100 function did not care about the bundles. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gk20a: share external bundles loading functionsAlexandre Courbot
There functions are going to be used by other chips that rely on NVIDIA-provided firmware. Export them. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gk20a: simplify external bundle loading functionsAlexandre Courbot
Make these functions easier to use by handling memory management from within. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gf100: load firmware in outer functionAlexandre Courbot
The firmwares required by GR may vary from chip to chip, especially with the introduction of secure boot and NVIDIA-provided firmwares. Move the firmware loading outside of gf100_gr_ctor so other chips may still call it while managing their firmwares themselves. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gk20a: move firmware bundle release to gf100Alexandre Courbot
Some members of gf100_gr were freed by the gk20a driver. That's not where it should be done - free them in gf100 so other chips that use NVIDIA-provided firmware free these structures properly. This also removes the need for a GK20A-specific destructor. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/core: add gpuobj memcpy helper functionsAlexandre Courbot
Add memcpy functions to copy a buffer to a gpuobj and vice-versa. This will be used by the secure boot code. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gm200: enable graphics deviceBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14drm/nouveau/gr/gm200: s/gm204/gm200/Ben Skeggs
Most of the per-chipset differences will go away when we fully switch to using the register lists provided by the firmware files, which will leave all the remaining code "belonging" to GM200. This is a preemptive rename from GM204 to GM200. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-17 21:51:35 +0000