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2021-06-18mtd: spinand: Add spinand_init_flash() helperPatrice Chotard
Add spinand_init_flash() helper which implement all needed init for future SPI-NAND resume ops. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210602094913.26472-3-patrice.chotard@foss.st.com
2021-06-18mtd: spinand: add spinand_read_cfg() helperPatrice Chotard
Put REG_CFG reading code in spinand_read_cfg(). This function will be needed by the future SPI-NAND resume ops. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210602094913.26472-2-patrice.chotard@foss.st.com
2021-06-18mtd: rawnand: marvell: add missing clk_disable_unprepare() on error in ↵Yang Yingliang
marvell_nfc_resume() Add clk_disable_unprepare() on error path in marvell_nfc_resume(). Fixes: bd9c3f9b3c00 ("mtd: rawnand: marvell: add suspend and resume hooks") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210601125814.3260364-1-yangyingliang@huawei.com
2021-06-18mtd: rawnand: arasan: Finer grain NV-DDR configurationMiquel Raynal
Add support for the timings register which may improve a bit the overall throughput. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084959.208804-2-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: arasan: Rename the data interface registerMiquel Raynal
There are 2 timing registers: - "data interface" - "timings" So far, the "data interface" register was named "timings" which begins misleading when bringing support for the "timings" register. Rename it to "data_iface". Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084959.208804-1-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: onfi: Fix endianness when reading NV-DDR valuesMiquel Raynal
Without the use of le16_to_cpu(), these accesses would have been wrong on a big-endian machine. Reported-by: kernel test robot <lkp@intel.com> Fixes: 45606518f961 ("mtd: rawnand: Add onfi_fill_nvddr_interface_config() helper") Fixes: 9310668fb60a ("mtd: rawnand: Retrieve NV-DDR timing modes from the ONFI parameter page") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210527084913.208635-1-miquel.raynal@bootlin.com
2021-06-18mtd: rawnand: arasan: Use the right DMA maskMiquel Raynal
Xilinx ZynqMP SoC and the Arasan controller support 64-bit DMA addressing. Define the right mask otherwise the default is 32 and some accesses may overflow the default mask. Reported-by: Jorge Courett <jorge.courett@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Jorge Courett <jorge.courett@gmail.com> Link: https://lore.kernel.org/linux-mtd/20210527084548.208429-1-miquel.raynal@bootlin.com
2021-06-11mtd: spinand: Fix double counting of ECC statsMiquel Raynal
In the raw NAND world, ECC engines increment ecc_stats and the final caller is responsible for returning -EBADMSG if the verification failed. In the SPI-NAND world it was a bit different until now because there was only one possible ECC engine: the on-die one. Indeed, the spinand_mtd_read() call was incrementing the ecc_stats counters depending on the outcome of spinand_check_ecc_status() directly. So now let's split the logic like this: - spinand_check_ecc_status() is specific to the SPI-NAND on-die engine and is kept very simple: it just returns the ECC status (bonus point: the content of this helper can be overloaded). - spinand_ondie_ecc_finish_io_req() is the caller of spinand_check_ecc_status() and will increment the counters and eventually return -EBADMSG. - spinand_mtd_read() is not tied to the on-die ECC implementation and should be able to handle results coming from other ECC engines: it has the responsibility of returning the maximum number of bitflips which happened during the entire operation as this is the only helper that is aware that several pages may be read in a row. Fixes: 945845b54c9c ("mtd: spinand: Instantiate a SPI-NAND on-die ECC engine") Reported-by: YouChing Lin <ycllin@mxic.com.tw> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: YouChing Lin <ycllin@mxic.com.tw> Link: https://lore.kernel.org/linux-mtd/20210527084345.208215-1-miquel.raynal@bootlin.com
2021-06-11Merge tag 'memory-controller-drv-pl353-5.14' into nand/nextMiquel Raynal
Memory controller drivers for v5.14 - PL353 Bigger work around ARM Primecell PL35x SMC memory controller driver by Miquel Raynal built on previous series from Naga Sureshkumar Relli. This includes bindings cleanup and correction, converting these to dtschema and several cleanyps in pl353-smc driver.
2021-06-10dt-binding: memory: pl353-smc: Convert to yamlMiquel Raynal
Convert this binding file to yaml schema. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-10-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10MAINTAINERS: Add PL353 SMC entryMiquel Raynal
Add Naga from Xilinx and myself responsible of this driver. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Link: https://lore.kernel.org/r/20210610082040.2075611-16-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10memory: pl353-smc: Declare variables following a reverse christmas tree orderMiquel Raynal
This is a purely cosmetic change. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20210610082040.2075611-15-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10memory: pl353-smc: Avoid useless acronyms in descriptionsMiquel Raynal
APER does not mean anything, while it seems legitimate to call this clock the AXI peripheral clock. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20210610082040.2075611-14-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10memory: pl353-smc: Let lower level controller drivers handle initsMiquel Raynal
There is no point in having all these definitions at the SMC bus level, these are extremely tight to the NAND controller driver implementation, are not particularly generic, imply more boilerplate than needed, do not really follow the device model by receiving no argument and some of them are actually buggy. Let's get rid of these right now as there is no current user and keep this driver at a simple level: only the SMC bare initializations. The NAND controller driver which I am going to introduce will take care of redefining properly all these helpers and using them directly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20210610082040.2075611-13-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10memory: pl353-smc: Rename goto labelsMiquel Raynal
A goto label is better named do_something: than out_something_to_do: Use the former wording and really describe what the jump involves. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20210610082040.2075611-12-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10memory: pl353-smc: Fix styleMiquel Raynal
Use proper spacing. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20210610082040.2075611-11-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10dt-binding: memory: pl353-smc: Fix the NAND controller node in the exampleMiquel Raynal
To be fully valid, the NAND controller node in the example should be named nand-controller instead of flash, should be at the address @0,0 instead of @e1000000 and should have a couple of: - #address-cells - #size-cells properties. The label is being renamed nfc0 as well which is more usual than nand_0. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-8-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10dt-binding: memory: pl353-smc: Drop unsupported nodes from the exampleMiquel Raynal
These nodes are given as examples and are not described nor used anywhere else. There is also no hardware of my knowledge compatible with these yet. If we want to be backward compatible, then we should avoid partially describing nodes and their content while there are no users. Plus, the examples are wrong (the addresses should be updated) so let's drop them before converting this file to yaml (only the NAND node, which will be fixed in the example and described somewhere else is kept). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-7-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10dt-binding: memory: pl353-smc: Fix the example syntax and styleMiquel Raynal
Enhance the spacing, the comment style, add { }, remove (...). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-6-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10dt-binding: memory: pl353-smc: Describe the child reg propertyMiquel Raynal
Each chil node should have a reg property, no matter the type of controller (NAND, NOR, SRAM). This should be part of the bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-5-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10dt-binding: memory: pl353-smc: Drop the partitioning sectionMiquel Raynal
This sentence does not belong to this file as this file describes the bus on which various controllers are wired to. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-4-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10dt-binding: memory: pl353-smc: Document the range propertyMiquel Raynal
The ranges property is missing in the description while actually used in the example. This property is actually needed, so mention it. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-3-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-06-10dt-binding: memory: pl353-smc: Rephrase the bindingMiquel Raynal
Reword this document before converting it to yaml. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210610082040.2075611-2-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-05-26mtd: spinand: macronix: Add support for serial NAND flashJaime Liao
Macronix NAND Flash devices are available in different configurations and densities. MX"35" means SPI NAND MX35"LF"/"UF" , LF means 3V and UF meands 1.8V MX35LF"2G" , 2G means 2Gbits MX35LF2G"E4"/"24"/"14", E4 means internal ECC and Quad I/O(x4) 24 means 8-bit ecc requirement and Quad I/O(x4) 14 means 4-bit ecc requirement and Quad I/O(x4) MX35LF2G14AC is 3V 2Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7926/MX35LF2G14AC,%203V,%202Gb,%20v1.1.pdf MX35UF4G24AD is 1.8V 4Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7980/MX35UF4G24AD,%201.8V,%204Gb,%20v0.00.pdf MX35UF4GE4AD/MX35UF2GE4AD are 1.8V 4G/2Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7983/MX35UF4GE4AD,%201.8V,%204Gb,%20v0.00.pdf MX35UF2GE4AC/MX35UF1GE4AC are 1.8V 2G/1Gbit serial NAND flash device with 8-bit on-die ECC https://www.mxic.com.tw/Lists/Datasheet/Attachments/7974/MX35UF2GE4AC,%201.8V,%202Gb,%20v1.0.pdf MX35UF2G14AC/MX35UF1G14AC are 1.8V 2G/1Gbit serial NAND flash device (without on-die ECC) https://www.mxic.com.tw/Lists/Datasheet/Attachments/7931/MX35UF2G14AC,%201.8V,%202Gb,%20v1.1.pdf Validated via normal(default) and QUAD mode by read, erase, read back, on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host(drivers/spi/spi-mxic.c). Signed-off-by: Jaime Liao <jaimeliao@mxic.com.tw> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1621475108-22523-1-git-send-email-jaimeliao@mxic.com.tw
2021-05-26mtd: rawnand: qcom: Delete an unneeded bool conversionZhen Lei
The result of an expression consisting of a single relational operator is already of the bool type and does not need to be evaluated explicitly. No functional change. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210510114944.3527-1-thunder.leizhen@huawei.com
2021-05-26mtd: rawnand: arasan: Leverage additional GPIO CSMiquel Raynal
Make use of the cs-gpios DT property as well as the core helper to parse it so that the Arasan controller driver can now assert many more chips than natively. The Arasan controller has an internal limitation: RB0 is tied to CS0 and RB1 is tied to CS1. Hence, it is possible to use external GPIOs as long as one or the other native CS is not used (or configured to be driven as a GPIO) and that all additional CS are physically wired on its corresponding RB line. Eg. CS0 is used as a native CS, CS1 is not used as native CS and may be used as a GPIO CS, CS2 is an additional GPIO CS. Then the target asserted by CS0 should also be wired to RB0, while the targets asserted by CS1 and CS2 should be wired to RB1. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-5-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: arasan: Ensure proper configuration for the asserted targetMiquel Raynal
The controller being always asserting one CS or the other, there is no need to actually select the right target before doing a page read/write. However, the anfc_select_target() helper actually also changes the timing configuration and clock in the case were two different NAND chips with different timing requirements would be used. In this situation, we must ensure proper configuration of the controller by calling it. As a consequence of this change, the anfc_select_target() helper is being moved earlier in the driver. Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-4-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Add a helper to parse the gpio-cs DT propertyMiquel Raynal
New chips may feature a lot of CS because of their extended length. As many controllers have been designed a decade ago, they usually only feature just a couple. This does not mean that the entire range of these chips cannot be accessed: it is just a matter of adding more GPIO CS in the hardware design. A DT property has been added to describe the CS array: cs-gpios. Here is the code parsing it this new property, allocating what needs to be, requesting the GPIOs and returning an array with the additional available CS. The first entries of this array are left empty and are reserved for native CS. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-3-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Move struct gpio_desc declaration to the topMiquel Raynal
The struct gpio_desc is declared in the middle of the rawnand.h header, right before the first function using it (nand_gpio_waitrdy). Before adding a new function and to make it clear: move the declaration to the top of the file. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210526093242.183847-2-miquel.raynal@bootlin.com
2021-05-26dt-binding: mtd: nand: Document the cs-gpios propertyMiquel Raynal
To reach higher capacities, arrays of chips are now pretty common. Unfortunately, most of the controllers have been designed a decade ago and did not all anticipate the need for several chip-selects. The new cs-gpios property allows to workaround this limitation by adding as many GPIO chip-select as needed. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/linux-mtd/20210510171800.27225-1-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: arasan: Support NV-DDR interfaceMiquel Raynal
Add support for the NV-DDR interface. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-23-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: arasan: Workaround a misbehaving prog type with NV-DDRMiquel Raynal
As explained in the comment introduced above the fix, the Arasan controller driver starts an operation when the prog register is being written with a "type" specific to the action to perform. The prog type used until now to perform a CHANGE READ COLUMN with an SDR interface was the PAGE READ type (CMD + ADDR + CMD + DATA). Unfortunately, for an unknown reason (let's call this a silicon bug) any CHANGE READ COLUMN performed this way in NV-DDR mode will fail: the data ready flag will never be triggered, nor will be the transfer complete flag. Forcefully, this leads to a timeout situation which is not easy to handle. Fortunately, it was spotted that sending the same commands through a different prog register "type", CHANGE READ COLUMN ENHANCED, would work all the time (even though this particular command is not supported by the core and is only available in a limited set of devices - we only care about the controller configuration and not the actual command which is sent to the device). So let's use this type instead when a CHANGE READ COLUMN is requested. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-22-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: arasan: Fix a macro parameterMiquel Raynal
This macro is not yet being used so the compilers never complained about it. Fix the macro before using it. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-21-miquel.raynal@bootlin.com
2021-05-26MAINTAINERS: Add myself as co-maintainer of the Arasan NAND controller driverMiquel Raynal
When I submitted the driver I added Naga as Maintainer and forgot to add myself. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-20-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Choose the best timings, NV-DDR includedMiquel Raynal
Now that the necessary peaces to support the NV-DDR interface type have been contributed, let's add the relevant logic to make use of it. In particular, the core does not choose the best SDR timings anymore but calls a more generic helper instead. This helper checks if NV-DDR is supported by trying to find the best NV-DDR supported mode through a logic very close to what is being done for SDR timings. If no NV-DDR mode in common between the NAND controller and the NAND chip is found, the core will fallback to SDR. Side note: theoretically, the data clock speed in NV-DDR mode 0 is slower than in SDR mode 5. In the situation where we would get a working NV-DDR mode 0, we could also try if SDR mode 5 is supported and eventually fallback to it in order to get the fastest possible throughput. However, in the field, it looks like most of the devices supporting NV-DDR avoid implementing the fastest SDR modes (like 4 and 5 EDO modes, which are a bit more complicated to handle than the other SDR modes). So, we will stick to the simplest logic: try NV-DDR otherwise fallback to SDR. If someone else experiences strong differences because of that we may still implement the logic defined above. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-19-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Allow SDR timings to be nackedMiquel Raynal
This should never happen in theory and is probably a controller driver bug. Anyway it's probably better to bail out at this point if this happens rather than continuing the boot process. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-18-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Support enabling NV-DDR through SET_FEATURESMiquel Raynal
Until now the parameter of the ADDR_TIMING_MODE feature was just the ONFI timing mode (from 0 to 5) because we were only supporting the SDR data interface. In the same byte, bits 4 and 5 indicate which data interface is being configured so use them to set the right mode and also read them back to ensure the right timing has been setup on the chip's side. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-17-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Add a helper to find the closest ONFI NV-DDR modeMiquel Raynal
Introduce a similar helper to onfi_find_closest_sdr_mode(), but for NV-DDR timings. It just takes a timing structure as parameter and returns the closest mode by comparing all minimum timings. This is useful for rigid controllers on which tuning the timings is not possible. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-16-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Handle the double bytes in NV-DDR modeMiquel Raynal
As explained in chapter "NV-DDR / NV-DDR2 / NV-DDR3 and Repeat Bytes" of the ONFI specification, with some commands (mainly the commands which do not transfer actual data) the data bytes are repeated twice and it is the responsibility of the receiver to discard them properly. The concerned commands are: SET_FEATURES, READ_ID, GET_FEATURES, READ_STATUS, READ_STATUS_ENHANCED, ODT_CONFIGURE. Hence, in the NAND core we are only impacted by the implementation of READ_ID, GET_FEATURES and READ_STATUS. The logic is the same for all: 2/ Check if it is relevant to read all data bytes twice. 1/ Allocate a buffer with twice the requested size (may be done statically). 2/ Update the instruction structure to read these extra bytes in the allocated buffer. 3/ Copy the even bytes into the original buffer. The performance hit is negligible on such small data transfers anyway and we don't really care about performances at this stage anyway. 4/ Free the allocated buffer, if any. Note: nand_data_read_op() is also impacted because it is theoretically possible to run the command/address cycles first, and, as another operation, do the data transfers. In this case we can easily identify the impacted commands because the force_8bit flag will be set (due to the same reason: their data does not go through the same pipeline). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-15-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Access SDR and NV-DDR timings through a common macroMiquel Raynal
Most timings related to the bus timings are different between SDR and NV-DDR. However, we identified 9 individual timings which are more related to the NAND chip internals. These are common between the two interface types. Fortunately, only these common timings are being shared through the NAND core and its ->exec_op() interface, which allows the writing of a simple macro checking the interface type and depending on it, returning either the relevant SDR timing or the NV-DDR timing. This is the purpose of the NAND_COMMON_TIMING_PS() macro. As all this is evaluated at build time, one will immediately be notified in case a non common timing is being accessed through this macro. Two handy macros are also inserted at the same time, which use PSEC_TO_NSEC or PSEC_TO_MSEC so that it is very easy to return timings in milli-, nano- or pico-seconds, as usually requested by the internal API. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-14-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Avoid accessing NV-DDR timings from legacy codeMiquel Raynal
Legacy code should not benefit from newer features, especially in helpers that have been deprecated for a very long time. People who want NV-DDR support must migrate their driver to the ->exec_op() API. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-13-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Add onfi_fill_nvddr_interface_config() helperMiquel Raynal
Same logic as for the SDR path, let's create a onfi_fill_nvddr_interface_config() helper to fill an interface configuration structure with NV-DDR timings, given a specific ONFI mode. There is one additional thing to do compared to SDR mode: tCAD timing can be fast or slow and this depends on an ONFI parameter page bit. By default the slow value is declared in the timings structure definition, but this helper can shrink it down if necessary. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-12-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Add an indirection on onfi_fill_interface_config()Miquel Raynal
This helper actually fills the interface configuration with SDR data. As part of the work to bring NV-DDR support, let's rename this helper onfi_fill_sdr_interface_config() and add a generic indirection to it. There are no functional changes here, but this will simplify a next change which adds onfi_fill_nvddr_interface_config() support. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-11-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Retrieve NV-DDR timing modes from the ONFI parameter pageMiquel Raynal
When parsing the ONFI parameter page, save the available NV-DDR timing modes in the core's dynamic ONFI structure. Once available to the rest of the core out of the ONFI driver, these values will then be used to derive the best timing mode. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-10-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Add NV-DDR timingsMiquel Raynal
Create the relevant ONFI NV-DDR timings structure and fill it with default values from the ONFI specification. Add the relevant structure entries and helpers. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-9-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Clarify the NV-DDR entries in the ONFI structureMiquel Raynal
Both src_sync_timing_mode and src_ssync_features entries of the ONFI parameter page have been updated and now are named nvddr_timing_modes, nvddr2_timing_modes and nvddr_nvddr2_features, which is much more understandable for someone which do not know the history of the ONFI specification. Update the relevant structure with regard to these changes. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-8-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Use more recent ONFI specification wordingMiquel Raynal
In particular, first ONFI specifications referred to SDR modes as asynchronous modes, which is not the term we usually have in mind. The spec has then been updated, so do the same here in the NAND subsystem to avoid any possible confusion. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-7-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: Update dead URLMiquel Raynal
The current link to the ONFI specification is broken, the onfi.org website now points to materials on Micron's website. Update the URL accordingly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-6-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: onfi: Use the BIT() macro when possibleMiquel Raynal
Update the onfi.h header to use the BIT() macro. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-5-miquel.raynal@bootlin.com
2021-05-26mtd: rawnand: atmel: Check the proposed data interface is supportedMiquel Raynal
Check the data interface is supported in ->setup_interface() before acknowledging the timings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-4-miquel.raynal@bootlin.com
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