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AgeCommit message (Expand)Author
2020-10-09drm/i915: Update gen12 multicast register rangesMatt Roper
2020-10-09drm/i915: Update gen12 forcewake tableMatt Roper
2020-10-09drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GTMatt Roper
2020-10-09drm/i915/display: Program PSR2 selective fetch registersJosé Roberto de Souza
2020-10-09drm/i915/display: Check PSR parameter and flag only in state compute phaseJosé Roberto de Souza
2020-10-09drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetchJosé Roberto de Souza
2020-10-09drm/i915/vbt: Add VRR VBT toggleJosé Roberto de Souza
2020-10-09drm/i915/vbt: Update the version and expected size of BDB_GENERAL_DEFINITIONS...José Roberto de Souza
2020-10-09drm/i915/vbt: Fix backlight parsing for VBT 234+José Roberto de Souza
2020-10-09drm/i915: s/int/u32/ for aux_offset/alignmentVille Syrjälä
2020-10-09drm/i915: Skip aux plane stuff when there is no aux planeVille Syrjälä
2020-10-09drm/i915: Set all unused color plane offsets to ~0xfff againVille Syrjälä
2020-10-09drm/i915: Rename i915_{save,restore}_state()Ville Syrjälä
2020-10-09drm/i915: Wait for VLV/CHV/BXT/GLK DSI panel power cycle delay on rebootVille Syrjälä
2020-10-09drm/i915: Wait for LVDS panel power cycle delay on rebootVille Syrjälä
2020-10-09drm/i915: Wait for eDP panel power cycle delay on reboot on all platformsVille Syrjälä
2020-10-09drm/i915: Replace the VLV/CHV eDP reboot notifier with the .shutdown() hookVille Syrjälä
2020-10-09drm/i915: Add an encoder .shutdown() hookVille Syrjälä
2020-10-09drm/i915: Shut down displays gracefully on rebootVille Syrjälä
2020-10-07drm/i915/dg1: provide port/phy mapping for vbtMatt Roper
2020-10-07drm/i915/dg1: Update comp master/slave relationships for PHYsMatt Roper
2020-10-07drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-DMatt Roper
2020-10-07drm/i915/dg1: gmbus pin mappingLucas De Marchi
2020-10-07drm/i915/dg1: Increase mmio size to 4MBVenkata Sandeep Dhanalakota
2020-10-07drm/i915/dg1: Define MOCS table for DG1Lucas De Marchi
2020-10-07drm/i915/dg1: Initialize RAWCLK properlyMatt Roper
2020-10-07drm/i915/dg1: add more PCI idsLucas De Marchi
2020-10-07drm/i915/display/ehl: Limit eDP to HBR2José Roberto de Souza
2020-10-06drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clockImre Deak
2020-10-06drm/i915: Add an encoder hook to sanitize its state during init/resumeImre Deak
2020-10-06drm/i915: Check for unsupported DP link rates during initial commitImre Deak
2020-10-06drm/i915: Move the initial fastset commit check to encoder hooksImre Deak
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak
2020-10-05drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper
2020-10-05drm/i915: don't conflate is_dgfx with fake lmemLucas De Marchi
2020-10-02drm/i915: Make lspcon_init() staticVille Syrjälä
2020-10-01drm/i915: Init lspcon after HPD in intel_dp_detect()Kai-Heng Feng
2020-10-01drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}Ville Syrjälä
2020-10-01drm/i915: Plumb crtc_state to link trainingVille Syrjälä
2020-10-01drm/i915: Split TGL DKL PHY buf trans per output typeVille Syrjälä
2020-10-01drm/i915: Split TGL combo PHY buf trans per output typeVille Syrjälä
2020-10-01drm/i915: Split EHL combo PHY buf trans per output typeVille Syrjälä
2020-10-01drm/i915: Split ICL MG PHY buf trans per output typeVille Syrjälä
2020-10-01drm/i915: Split ICL combo PHY buf trans per output typeVille Syrjälä
2020-10-01drm/i915: Shove the PHY test into the hotplug workVille Syrjälä
2020-10-01drm/i915: Make intel_dp_process_phy_request() staticVille Syrjälä
2020-10-01drm/i915: s/old_crtc_state/crtc_state/Ville Syrjälä
2020-10-01drm/i915: s/pre_empemph/preemph/Ville Syrjälä
2020-10-01drm/i915: Fix TGL DKL PHY DP vswing handlingVille Syrjälä
2020-10-01drm/i915: Implement display WA #1142:kbl,cfl,cmlVille Syrjälä
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