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-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h (renamed from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h)0
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h (renamed from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h)0
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h (renamed from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h)0
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h6
4 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h
index 1a3c4864ae66..1a3c4864ae66 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h
index 6af3e6fa2f23..6af3e6fa2f23 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h
index b8cadcf78da6..b8cadcf78da6 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
index 5fb38f611554..ae59a3fdea8a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h
@@ -33,9 +33,9 @@
#include "asic_reg/nbio/nbio_7_0_offset.h"
#include "asic_reg/nbio/nbio_7_0_sh_mask.h"
-#include "asic_reg/raven1/THM/thm_10_0_default.h"
-#include "asic_reg/raven1/THM/thm_10_0_offset.h"
-#include "asic_reg/raven1/THM/thm_10_0_sh_mask.h"
+#include "asic_reg/thm/thm_10_0_default.h"
+#include "asic_reg/thm/thm_10_0_offset.h"
+#include "asic_reg/thm/thm_10_0_sh_mask.h"
#define ixDDI_PHY_GEN_STATUS 0x3FCE8