diff options
Diffstat (limited to 'drivers/staging')
| -rw-r--r-- | drivers/staging/rtl8192u/ieee80211/ieee80211.h | 10 | ||||
| -rw-r--r-- | drivers/staging/rtl8192u/ieee80211/rtl819x_Qos.h | 49 | ||||
| -rw-r--r-- | drivers/staging/rtl8192u/r8192U.h | 95 | ||||
| -rw-r--r-- | drivers/staging/rtl8192u/r8192U_core.c | 12 | ||||
| -rw-r--r-- | drivers/staging/rtl8192u/r8192U_dm.c | 17 | ||||
| -rw-r--r-- | drivers/staging/rtl8192u/r8192U_hw.h | 145 | ||||
| -rw-r--r-- | drivers/staging/rtl8192u/r819xU_cmdpkt.h | 6 | ||||
| -rw-r--r-- | drivers/staging/rtl8192u/r819xU_phy.c | 4 |
8 files changed, 139 insertions, 199 deletions
diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211.h b/drivers/staging/rtl8192u/ieee80211/ieee80211.h index d481a26c25ae..967ef9a98fc0 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211.h @@ -415,7 +415,7 @@ typedef struct ieee_param { /* QOS control */ #define IEEE80211_QCTL_TID 0x000F -#define FC_QOS_BIT BIT7 +#define FC_QOS_BIT BIT(7) #define IsDataFrame(pdu) ( ((pdu[0] & 0x0C)==0x08) ? true : false ) #define IsLegacyDataFrame(pdu) (IsDataFrame(pdu) && (!(pdu[0]&FC_QOS_BIT)) ) //added by wb. Is this right? @@ -1565,10 +1565,10 @@ typedef struct _RT_POWER_SAVE_CONTROL { } RT_POWER_SAVE_CONTROL, *PRT_POWER_SAVE_CONTROL; typedef u32 RT_RF_CHANGE_SOURCE; -#define RF_CHANGE_BY_SW BIT31 -#define RF_CHANGE_BY_HW BIT30 -#define RF_CHANGE_BY_PS BIT29 -#define RF_CHANGE_BY_IPS BIT28 +#define RF_CHANGE_BY_SW BIT(31) +#define RF_CHANGE_BY_HW BIT(30) +#define RF_CHANGE_BY_PS BIT(29) +#define RF_CHANGE_BY_IPS BIT(28) #define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17. typedef enum diff --git a/drivers/staging/rtl8192u/ieee80211/rtl819x_Qos.h b/drivers/staging/rtl8192u/ieee80211/rtl819x_Qos.h index 9fbce912a74b..49c23c720f78 100644 --- a/drivers/staging/rtl8192u/ieee80211/rtl819x_Qos.h +++ b/drivers/staging/rtl8192u/ieee80211/rtl819x_Qos.h @@ -1,39 +1,6 @@ #ifndef __INC_QOS_TYPE_H #define __INC_QOS_TYPE_H -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - #define MAX_WMMELE_LENGTH 64 // @@ -375,17 +342,17 @@ typedef struct _ACM{ typedef u8 AC_UAPSD, *PAC_UAPSD; -#define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0) -#define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0) +#define GET_VO_UAPSD(_apsd) ((_apsd) & BIT(0)) +#define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT(0)) -#define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1) -#define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1) +#define GET_VI_UAPSD(_apsd) ((_apsd) & BIT(1)) +#define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT(1)) -#define GET_BK_UAPSD(_apsd) ((_apsd) & BIT2) -#define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT2) +#define GET_BK_UAPSD(_apsd) ((_apsd) & BIT(2)) +#define SET_BK_UAPSD(_apsd) ((_apsd) |= BIT(2)) -#define GET_BE_UAPSD(_apsd) ((_apsd) & BIT3) -#define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT3) +#define GET_BE_UAPSD(_apsd) ((_apsd) & BIT(3)) +#define SET_BE_UAPSD(_apsd) ((_apsd) |= BIT(3)) //typedef struct _TCLASS{ diff --git a/drivers/staging/rtl8192u/r8192U.h b/drivers/staging/rtl8192u/r8192U.h index a76748e3b506..ee1c72267811 100644 --- a/drivers/staging/rtl8192u/r8192U.h +++ b/drivers/staging/rtl8192u/r8192U.h @@ -43,39 +43,6 @@ #define MAX_KEY_LEN 61 #define KEY_BUF_SIZE 5 -#define BIT0 0x00000001 -#define BIT1 0x00000002 -#define BIT2 0x00000004 -#define BIT3 0x00000008 -#define BIT4 0x00000010 -#define BIT5 0x00000020 -#define BIT6 0x00000040 -#define BIT7 0x00000080 -#define BIT8 0x00000100 -#define BIT9 0x00000200 -#define BIT10 0x00000400 -#define BIT11 0x00000800 -#define BIT12 0x00001000 -#define BIT13 0x00002000 -#define BIT14 0x00004000 -#define BIT15 0x00008000 -#define BIT16 0x00010000 -#define BIT17 0x00020000 -#define BIT18 0x00040000 -#define BIT19 0x00080000 -#define BIT20 0x00100000 -#define BIT21 0x00200000 -#define BIT22 0x00400000 -#define BIT23 0x00800000 -#define BIT24 0x01000000 -#define BIT25 0x02000000 -#define BIT26 0x04000000 -#define BIT27 0x08000000 -#define BIT28 0x10000000 -#define BIT29 0x20000000 -#define BIT30 0x40000000 -#define BIT31 0x80000000 - #define Rx_Smooth_Factor 20 #define DMESG(x, a...) #define DMESGW(x, a...) @@ -87,44 +54,44 @@ extern u32 rt_global_debug_component; pr_debug("RTL8192U: " x "\n", ##args); \ } while (0) -#define COMP_TRACE BIT0 /* Function call tracing. */ -#define COMP_DBG BIT1 -#define COMP_INIT BIT2 /* Driver initialization/halt/reset. */ +#define COMP_TRACE BIT(0) /* Function call tracing. */ +#define COMP_DBG BIT(1) +#define COMP_INIT BIT(2) /* Driver initialization/halt/reset. */ -#define COMP_RECV BIT3 /* Receive data path. */ -#define COMP_SEND BIT4 /* Send data path. */ -#define COMP_IO BIT5 +#define COMP_RECV BIT(3) /* Receive data path. */ +#define COMP_SEND BIT(4) /* Send data path. */ +#define COMP_IO BIT(5) /* 802.11 Power Save mode or System/Device Power state. */ -#define COMP_POWER BIT6 +#define COMP_POWER BIT(6) /* 802.11 link related: join/start BSS, leave BSS. */ -#define COMP_EPROM BIT7 -#define COMP_SWBW BIT8 /* Bandwidth switch. */ -#define COMP_POWER_TRACKING BIT9 /* 8190 TX Power Tracking */ -#define COMP_TURBO BIT10 /* Turbo Mode */ -#define COMP_QOS BIT11 -#define COMP_RATE BIT12 /* Rate Adaptive mechanism */ -#define COMP_RM BIT13 /* Radio Measurement */ -#define COMP_DIG BIT14 -#define COMP_PHY BIT15 -#define COMP_CH BIT16 /* Channel setting debug */ -#define COMP_TXAGC BIT17 /* Tx power */ -#define COMP_HIPWR BIT18 /* High Power Mechanism */ -#define COMP_HALDM BIT19 /* HW Dynamic Mechanism */ -#define COMP_SEC BIT20 /* Event handling */ -#define COMP_LED BIT21 -#define COMP_RF BIT22 -#define COMP_RXDESC BIT23 /* Rx desc information for SD3 debug */ +#define COMP_EPROM BIT(7) +#define COMP_SWBW BIT(8) /* Bandwidth switch. */ +#define COMP_POWER_TRACKING BIT(9) /* 8190 TX Power Tracking */ +#define COMP_TURBO BIT(10) /* Turbo Mode */ +#define COMP_QOS BIT(11) +#define COMP_RATE BIT(12) /* Rate Adaptive mechanism */ +#define COMP_RM BIT(13) /* Radio Measurement */ +#define COMP_DIG BIT(14) +#define COMP_PHY BIT(15) +#define COMP_CH BIT(16) /* Channel setting debug */ +#define COMP_TXAGC BIT(17) /* Tx power */ +#define COMP_HIPWR BIT(18) /* High Power Mechanism */ +#define COMP_HALDM BIT(19) /* HW Dynamic Mechanism */ +#define COMP_SEC BIT(20) /* Event handling */ +#define COMP_LED BIT(21) +#define COMP_RF BIT(22) +#define COMP_RXDESC BIT(23) /* Rx desc information for SD3 debug */ /* 11n or 8190 specific code */ -#define COMP_FIRMWARE BIT24 /* Firmware downloading */ -#define COMP_HT BIT25 /* 802.11n HT related information */ -#define COMP_AMSDU BIT26 /* A-MSDU Debugging */ -#define COMP_SCAN BIT27 -#define COMP_DOWN BIT29 /* rm driver module */ -#define COMP_RESET BIT30 /* Silent reset */ -#define COMP_ERR BIT31 /* Error out, always on */ +#define COMP_FIRMWARE BIT(24) /* Firmware downloading */ +#define COMP_HT BIT(25) /* 802.11n HT related information */ +#define COMP_AMSDU BIT(26) /* A-MSDU Debugging */ +#define COMP_SCAN BIT(27) +#define COMP_DOWN BIT(29) /* rm driver module */ +#define COMP_RESET BIT(30) /* Silent reset */ +#define COMP_ERR BIT(31) /* Error out, always on */ #define RTL819x_DEBUG #ifdef RTL819x_DEBUG diff --git a/drivers/staging/rtl8192u/r8192U_core.c b/drivers/staging/rtl8192u/r8192U_core.c index eab0d811e85a..678ecf6d2b79 100644 --- a/drivers/staging/rtl8192u/r8192U_core.c +++ b/drivers/staging/rtl8192u/r8192U_core.c @@ -233,7 +233,7 @@ static void CamResetAllEntry(struct net_device *dev) * condition, Cam can not be reset because upper layer will not set * this static key again. */ - ulcommand |= BIT31 | BIT30; + ulcommand |= BIT(31) | BIT(30); write_nic_dword(dev, RWCAM, ulcommand); } @@ -242,7 +242,7 @@ static void CamResetAllEntry(struct net_device *dev) void write_cam(struct net_device *dev, u8 addr, u32 data) { write_nic_dword(dev, WCAMI, data); - write_nic_dword(dev, RWCAM, BIT31 | BIT16 | (addr & 0xff)); + write_nic_dword(dev, RWCAM, BIT(31) | BIT(16) | (addr & 0xff)); } u32 read_cam(struct net_device *dev, u8 addr) @@ -2412,7 +2412,7 @@ static void rtl8192_get_eeprom_size(struct net_device *dev) read_nic_word_E(dev, EPROM_CMD, &curCR); RT_TRACE(COMP_EPROM, "read from Reg EPROM_CMD(%x):%x\n", EPROM_CMD, curCR); - /* whether need I consider BIT5? */ + /* whether need I consider BIT(5?) */ priv->epromtype = (curCR & Cmd9346CR_9356SEL) ? EPROM_93c56 : EPROM_93c46; RT_TRACE(COMP_EPROM, @@ -5180,14 +5180,14 @@ void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, dev, EntryNo, KeyIndex, KeyType, MacAddr); if (DefaultKey) - usConfig |= BIT15 | (KeyType << 2); + usConfig |= BIT(15) | (KeyType << 2); else - usConfig |= BIT15 | (KeyType << 2) | KeyIndex; + usConfig |= BIT(15) | (KeyType << 2) | KeyIndex; for (i = 0; i < CAM_CONTENT_COUNT; i++) { TargetCommand = i + CAM_CONTENT_COUNT * EntryNo; - TargetCommand |= BIT31 | BIT16; + TargetCommand |= BIT(31) | BIT(16); if (i == 0) { /* MAC|Config */ TargetContent = (u32)(*(MacAddr + 0)) << 16 | diff --git a/drivers/staging/rtl8192u/r8192U_dm.c b/drivers/staging/rtl8192u/r8192U_dm.c index 5277f2eec033..375ec96b9469 100644 --- a/drivers/staging/rtl8192u/r8192U_dm.c +++ b/drivers/staging/rtl8192u/r8192U_dm.c @@ -325,21 +325,26 @@ static void dm_check_rate_adaptive(struct net_device *dev) (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz); pra->upper_rssi_threshold_ratr = - (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0); + (pra->upper_rssi_threshold_ratr & (~BIT(31))) | + ((bshort_gi_enabled) ? BIT(31) : 0); pra->middle_rssi_threshold_ratr = - (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0); + (pra->middle_rssi_threshold_ratr & (~BIT(31))) | + ((bshort_gi_enabled) ? BIT(31) : 0); if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) { pra->low_rssi_threshold_ratr = - (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0); + (pra->low_rssi_threshold_ratr_40M & (~BIT(31))) | + ((bshort_gi_enabled) ? BIT(31) : 0); } else { pra->low_rssi_threshold_ratr = - (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0); + (pra->low_rssi_threshold_ratr_20M & (~BIT(31))) | + ((bshort_gi_enabled) ? BIT(31) : 0); } /* cosa add for test */ pra->ping_rssi_ratr = - (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled) ? BIT31:0); + (pra->ping_rssi_ratr & (~BIT(31))) | + ((bshort_gi_enabled) ? BIT(31) : 0); /* 2007/10/08 MH We support RA smooth scheme now. When it is the first time to link with AP. We will not change upper/lower threshold. If @@ -2378,7 +2383,7 @@ static void dm_check_pbc_gpio(struct net_device *dev) if (tmp1byte == 0xff) return; - if (tmp1byte&BIT6 || tmp1byte&BIT0) { + if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) { /* * Here we only set bPbcPressed to TRUE * After trigger PBC, the variable will be set to FALSE diff --git a/drivers/staging/rtl8192u/r8192U_hw.h b/drivers/staging/rtl8192u/r8192U_hw.h index a93694ff0c42..e07d65d04dbc 100644 --- a/drivers/staging/rtl8192u/r8192U_hw.h +++ b/drivers/staging/rtl8192u/r8192U_hw.h @@ -55,17 +55,17 @@ typedef enum _BaseBand_Config_Type{ #define BB_ANTATTEN_CHAN14 0x0c #define BB_ANTENNA_B 0x40 -#define BB_HOST_BANG (1<<30) -#define BB_HOST_BANG_EN (1<<2) -#define BB_HOST_BANG_CLK (1<<1) -#define BB_HOST_BANG_RW (1<<3) +#define BB_HOST_BANG BIT(30) +#define BB_HOST_BANG_EN BIT(2) +#define BB_HOST_BANG_CLK BIT(1) +#define BB_HOST_BANG_RW BIT(3) #define BB_HOST_BANG_DATA 1 //#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920) #define AFR 0x010 -#define AFR_CardBEn (1<<0) -#define AFR_CLKRUN_SEL (1<<1) -#define AFR_FuncRegEn (1<<2) +#define AFR_CardBEn BIT(0) +#define AFR_CLKRUN_SEL BIT(1) +#define AFR_FuncRegEn BIT(2) #define RTL8190_EEPROM_ID 0x8129 #define EEPROM_VID 0x02 #define EEPROM_PID 0x04 @@ -126,38 +126,39 @@ enum _RTL8192Usb_HW { #define TCR_LRL_OFFSET 0 #define TCR_SRL_OFFSET 8 #define TCR_MXDMA_OFFSET 21 -#define TCR_SAT BIT24 // Enable Rate depedent ack timeout timer +#define TCR_SAT BIT(24) // Enable Rate depedent ack timeout timer RCR = 0x044, // Receive Configuration Register -#define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \ - (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23)) -#define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15)) +#define MAC_FILTER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | \ + BIT(12) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \ + BIT(22) | BIT(23)) +#define RX_FIFO_THRESHOLD_MASK (BIT(13) | BIT(14) | BIT(15)) #define RX_FIFO_THRESHOLD_SHIFT 13 #define RX_FIFO_THRESHOLD_128 3 #define RX_FIFO_THRESHOLD_256 4 #define RX_FIFO_THRESHOLD_512 5 #define RX_FIFO_THRESHOLD_1024 6 #define RX_FIFO_THRESHOLD_NONE 7 -#define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) +#define MAX_RX_DMA_MASK (BIT(8) | BIT(9) | BIT(10)) #define RCR_MXDMA_OFFSET 8 #define RCR_FIFO_OFFSET 13 -#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size. -#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2 -#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1 -#define RCR_ENMBID BIT27 // Enable Multiple BssId. -#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames -#define RCR_CBSSID BIT23 // Accept BSSID match packet -#define RCR_APWRMGT BIT22 // Accept power management packet -#define RCR_ADD3 BIT21 // Accept address 3 match packet -#define RCR_AMF BIT20 // Accept management type frame -#define RCR_ACF BIT19 // Accept control type frame -#define RCR_ADF BIT18 // Accept data type frame -#define RCR_RXFTH BIT13 // Rx FIFO Threshold -#define RCR_AICV BIT12 // Accept ICV error packet -#define RCR_ACRC32 BIT5 // Accept CRC32 error packet -#define RCR_AB BIT3 // Accept broadcast packet -#define RCR_AM BIT2 // Accept multicast packet -#define RCR_APM BIT1 // Accept physical match packet -#define RCR_AAP BIT0 // Accept all unicast packet +#define RCR_ONLYERLPKT BIT(31) // Early Receiving based on Packet Size. +#define RCR_ENCS2 BIT(30) // Enable Carrier Sense Detection Method 2 +#define RCR_ENCS1 BIT(29) // Enable Carrier Sense Detection Method 1 +#define RCR_ENMBID BIT(27) // Enable Multiple BssId. +#define RCR_ACKTXBW (BIT(24) | BIT(25)) // TXBW Setting of ACK frames +#define RCR_CBSSID BIT(23) // Accept BSSID match packet +#define RCR_APWRMGT BIT(22) // Accept power management packet +#define RCR_ADD3 BIT(21) // Accept address 3 match packet +#define RCR_AMF BIT(20) // Accept management type frame +#define RCR_ACF BIT(19) // Accept control type frame +#define RCR_ADF BIT(18) // Accept data type frame +#define RCR_RXFTH BIT(13) // Rx FIFO Threshold +#define RCR_AICV BIT(12) // Accept ICV error packet +#define RCR_ACRC32 BIT(5) // Accept CRC32 error packet +#define RCR_AB BIT(3) // Accept broadcast packet +#define RCR_AM BIT(2) // Accept multicast packet +#define RCR_APM BIT(1) // Accept physical match packet +#define RCR_AAP BIT(0) // Accept all unicast packet SLOT_TIME = 0x049, // Slot Time Register ACK_TIMEOUT = 0x04c, // Ack Timeout Register PIFS_TIME = 0x04d, // PIFS time @@ -180,12 +181,12 @@ enum _RTL8192Usb_HW { WCAMI = 0x0A4, // Software write CAM input content RCAMO = 0x0A8, // Software read/write CAM config SECR = 0x0B0, //Security Configuration Register -#define SCR_TxUseDK BIT0 //Force Tx Use Default Key -#define SCR_RxUseDK BIT1 //Force Rx Use Default Key -#define SCR_TxEncEnable BIT2 //Enable Tx Encryption -#define SCR_RxDecEnable BIT3 //Enable Rx Decryption -#define SCR_SKByA2 BIT4 //Search kEY BY A2 -#define SCR_NoSKMC BIT5 //No Key Search for Multicast +#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key +#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key +#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption +#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption +#define SCR_SKByA2 BIT(4) //Search kEY BY A2 +#define SCR_NoSKMC BIT(5) //No Key Search for Multicast #define SCR_UseDK 0x01 #define SCR_TxSecEnable 0x02 #define SCR_RxSecEnable 0x04 @@ -226,13 +227,13 @@ enum _RTL8192Usb_HW { //// 8190 AcmHwCtrl bits (offset 0x171, 1 byte) ////---------------------------------------------------------------------------- // -#define AcmHw_HwEn BIT0 -#define AcmHw_BeqEn BIT1 -#define AcmHw_ViqEn BIT2 -#define AcmHw_VoqEn BIT3 -#define AcmHw_BeqStatus BIT4 -#define AcmHw_ViqStatus BIT5 -#define AcmHw_VoqStatus BIT6 +#define AcmHw_HwEn BIT(0) +#define AcmHw_BeqEn BIT(1) +#define AcmHw_ViqEn BIT(2) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) +#define AcmHw_ViqStatus BIT(5) +#define AcmHw_VoqStatus BIT(6) AcmFwCtrl = 0x172, // ACM Firmware Control Register AES_11N_FIX = 0x173, @@ -281,18 +282,18 @@ enum _RTL8192Usb_HW { NHM_RPI_COUNTER5 = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5]. NHM_RPI_COUNTER6 = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6]. NHM_RPI_COUNTER7 = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7]. -#define BW_OPMODE_11J BIT0 -#define BW_OPMODE_5G BIT1 -#define BW_OPMODE_20MHZ BIT2 +#define BW_OPMODE_11J BIT(0) +#define BW_OPMODE_5G BIT(1) +#define BW_OPMODE_20MHZ BIT(2) BW_OPMODE = 0x300, // Bandwidth operation mode MSR = 0x303, // Media Status register -#define MSR_LINK_MASK ((1<<0)|(1<<1)) +#define MSR_LINK_MASK (BIT(0)|BIT(1)) #define MSR_LINK_MANAGED 2 #define MSR_LINK_NONE 0 #define MSR_LINK_SHIFT 0 #define MSR_LINK_ADHOC 1 #define MSR_LINK_MASTER 3 -#define MSR_LINK_ENEDCA (1<<4) +#define MSR_LINK_ENEDCA BIT(4) RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long #define RETRY_LIMIT_SHORT_SHIFT 8 #define RETRY_LIMIT_LONG_SHIFT 0 @@ -304,27 +305,27 @@ enum _RTL8192Usb_HW { #define RRSR_RSC_LOWSUBCHNL 0x400000 #define RRSR_RSC_UPSUBCHANL 0x200000 #define RRSR_SHORT 0x800000 -#define RRSR_1M BIT0 -#define RRSR_2M BIT1 -#define RRSR_5_5M BIT2 -#define RRSR_11M BIT3 -#define RRSR_6M BIT4 -#define RRSR_9M BIT5 -#define RRSR_12M BIT6 -#define RRSR_18M BIT7 -#define RRSR_24M BIT8 -#define RRSR_36M BIT9 -#define RRSR_48M BIT10 -#define RRSR_54M BIT11 -#define RRSR_MCS0 BIT12 -#define RRSR_MCS1 BIT13 -#define RRSR_MCS2 BIT14 -#define RRSR_MCS3 BIT15 -#define RRSR_MCS4 BIT16 -#define RRSR_MCS5 BIT17 -#define RRSR_MCS6 BIT18 -#define RRSR_MCS7 BIT19 -#define BRSR_AckShortPmb BIT23 // CCK ACK: use Short Preamble or not. +#define RRSR_1M BIT(0) +#define RRSR_2M BIT(1) +#define RRSR_5_5M BIT(2) +#define RRSR_11M BIT(3) +#define RRSR_6M BIT(4) +#define RRSR_9M BIT(5) +#define RRSR_12M BIT(6) +#define RRSR_18M BIT(7) +#define RRSR_24M BIT(8) +#define RRSR_36M BIT(9) +#define RRSR_48M BIT(10) +#define RRSR_54M BIT(11) +#define RRSR_MCS0 BIT(12) +#define RRSR_MCS1 BIT(13) +#define RRSR_MCS2 BIT(14) +#define RRSR_MCS3 BIT(15) +#define RRSR_MCS4 BIT(16) +#define RRSR_MCS5 BIT(17) +#define RRSR_MCS6 BIT(18) +#define RRSR_MCS7 BIT(19) +#define BRSR_AckShortPmb BIT(23) // CCK ACK: use Short Preamble or not. RATR0 = 0x320, // Rate Adaptive Table register1 UFWP = 0x318, DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI @@ -380,10 +381,10 @@ enum _RTL8192Usb_HW { MacBlkCtrl = 0x403, // Mac block on/off control register EPROM_CMD = 0xfe58, -#define Cmd9346CR_9356SEL (1<<4) -#define EPROM_CMD_RESERVED_MASK (1<<5) +#define Cmd9346CR_9356SEL BIT(4) +#define EPROM_CMD_RESERVED_MASK BIT(5) #define EPROM_CMD_OPERATING_MODE_SHIFT 6 -#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) +#define EPROM_CMD_OPERATING_MODE_MASK (BIT(7) | BIT(6)) #define EPROM_CMD_CONFIG 0x3 #define EPROM_CMD_NORMAL 0 #define EPROM_CMD_LOAD 1 diff --git a/drivers/staging/rtl8192u/r819xU_cmdpkt.h b/drivers/staging/rtl8192u/r819xU_cmdpkt.h index cc8029a15df4..f490e253ee50 100644 --- a/drivers/staging/rtl8192u/r819xU_cmdpkt.h +++ b/drivers/staging/rtl8192u/r819xU_cmdpkt.h @@ -9,9 +9,9 @@ #define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t) /* 2008/05/08 amy For USB constant. */ -#define ISR_TxBcnOk BIT27 /* Transmit Beacon OK */ -#define ISR_TxBcnErr BIT26 /* Transmit Beacon Error */ -#define ISR_BcnTimerIntr BIT13 /* Beacon Timer Interrupt */ +#define ISR_TxBcnOk BIT(27) /* Transmit Beacon OK */ +#define ISR_TxBcnErr BIT(26) /* Transmit Beacon Error */ +#define ISR_BcnTimerIntr BIT(13) /* Beacon Timer Interrupt */ /* Define element ID of command packet. */ diff --git a/drivers/staging/rtl8192u/r819xU_phy.c b/drivers/staging/rtl8192u/r819xU_phy.c index e5dbaca9e518..70656441c145 100644 --- a/drivers/staging/rtl8192u/r819xU_phy.c +++ b/drivers/staging/rtl8192u/r819xU_phy.c @@ -1110,7 +1110,7 @@ bool rtl8192_SetRFPowerState(struct net_device *dev, case eRfOn: /* RF-A, RF-B */ /* enable RF-Chip A/B - 0x860[4] */ - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 0x1); /* analog to digital on - 0x88c[9:8] */ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, @@ -1135,7 +1135,7 @@ bool rtl8192_SetRFPowerState(struct net_device *dev, case eRfOff: /* RF-A, RF-B */ /* disable RF-Chip A/B - 0x860[4] */ - rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, + rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 0x0); /* analog to digital off, for power save */ rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, |